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IDL - IDLE Sequence Status Changed
A change in the status of the serial line was detected on the HDLC channel.
The SCC status register may be read to determine the current status.
TXE - Tx Error
An error (CTS lost or underrun) occurred on the transmitter channel.
RXF - Rx Frame
A complete frame has been received on the HDLC channel.
BSY - Busy Condition
A frame was received and discarded due to lack of buffers.
TXB - Tx Buffer
A buffer has been transmitted on the HDLC channel.
RXB - Rx Buffer
A buffer has been received on the HDLC channel.
4.5.12.13 HDLC MASK REGISTER.
The SCC mask register (SCCM) is referred to
as the HDLC mask register when the SCC is operating as an HDLC controller.
It is an 8-bit read-write register that has the same bit formats as the HDLC
event register. If a bit in the HDLC mask register is a one, the corresponding
interrupt in the event register will be enabled. If the bit is zero, the corre-
sponding interrupt in the event register will be masked.
4.5.13 BISYNC Controller
4-66
By appropriately setting the SCC mode register, any of the SCC channels
may be configured to function as a BISYNCcontroller. The BISYNC controller
handles the basic functions of the BISYNC protocol in normal mode and in
transparent mode.
The SCC in BISYNC mode can work with IDL, GCI (IOM2), PCM highway, or
NMSI interfaces. When the SCC in BISYNC mode is used with a modem
interface (NMSI), the SCC outputs are connected directly to the external pins.
The modem interface uses seven dedicated pins: transmit data (TXD), receive
data (RXD) receive clock (RCLK), transmit clock (TCLK), carrier detect (CD),
clear to send (CTS), and request to send (RTS). Other modem lines can be
supported using the parallel
1/0
pins.
MC68302 USER'S MANUAL
MOTOROLA
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