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MC68302
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Motorola MC68302 User Manual
Integrated multi-protocol processor
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User manual
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Contents
Table of Contents
Bookmarks
Table of Contents
Table of Contents
Block Diagram
General Description
Features
MC68302 System Architecture
NMSI Communications-Oriented Environment
Basic Rate ISDN or Digital Voice/Data Terminal
Programming Model
MC68000/MC68008 Core
Instruction Set Summary
Address Spaces
Exception Processing
Exception Vectors
Exception Stacking Order
Interrupt Processing
M68000 Signal Differences
MC68302 IMP Configuration Control
MC68302 Memory Map
System Integration Block (SIB)
Key Features
IDMA Registers
Channel Mode Register (CMR)
Source Address Pointer Register (SAPR)
Destination Address Pointer Register (DAPR)
Function Code Register (FCR)
Byte Count Register (BCR)
Channel Status Register (CSR)
Interface Signals
DREQ and DACK
Done
IDMA Operational Description
Channel Initialization
Data Transfer
Address Sequencing
Transfer Request Generation
Block Transfer Termination
IDMA Programming
OMA Bus Arbitration
Bus Exceptions
Reset
Bus Error
Halt
Retry
Interrupt Controller
Operation
Interrupt Priorities
INRQ and EXRQ Priority Levels
INRQ Interrupt Source Priorities
Nested Interrupts
Masking Interrupt Sources and Events
Interrupt Vector Generation
Interrupt Controller Programming Model
Global Interrupt Mode Register (GIMR)
Interrupt Pending Register (IPR)
Interrupt Mask Register (IMR)
Interrupt In-Service Register (ISR)
Parallel Ports
Port a
Port B
Pb7-Pbo
Pb11-Pb8
1/0 Port Registers
Dual-Port RAM
Timers
Timer Key Features
General-Purpose Timer Units
Timer Reference Registers (TRR1, TRR2)
Timer Capture Registers (TCR1, TCR2)
Timer Counter (Tcnl, TCN2)
Timer Event Registers (TER1, TER2)
Watchdog Timer
Watchdog Timer Operation
Watchdog Reference Register (WRR)
Watchdog Counter (WCN)
External Chip-Select Signals and Wait-State Logic
Chip-Select Logic Key Features
Chip-Select Registers
Base Register (BR3-BRO)
Option Registers (OR3-0RO)
On-Chip Clock Generator
System Control
System Control Register (SCR)
System Status Bus
System Control Bits
Disable CPU Logic (M68000)
Bus Arbitration Logic
Hardware Watchdog
Low-Power (Standby) Modes
Freeze Control
Main Controller
SDMA Channels
Communications Processor (CP)
Command Set
Serial Channels Physical Interface
IDL Interface
GCI Interface
PCM Highway Mode
Nonmultiplexed Serial Interface (NMSI)
Serial Interface Registers
Serial Interface Mode Register (Simode)
Serial Communication Controllers (Sccs)
SCC Features
SCC Configuration Register (SCON)
Asynchronous Baud Rate Generator Examples
Synchronous Baud Rate Generator Examples
SCC Mode Register (SCM)
SCC Data Synchronization Register (DSR)
Buffer Descriptors Table
SCC Parameter RAM Memory Map
Data Buffer Function Code Register (TFCR, RFCR)
Maximum Receive Buffer Length Register (MRBLR)
Receiver Buffer Descriptor Number (RBD#)
Transmit Buffer Descriptor Number (TBD#)
SCC Initialization
Interrupt Mechanism
SCC Event Register (SCCE)
SCC Mask Register (SCCM)
SCC Status Register (SCCS)
SCC Transparent Mode Support
Power Saving with Sccs
UART Controller
Normal Asynchronous Mode
Asynchronous DDCMP Mode
UART Memory Map
UART Programming Model
UART Command Set
UART Address Recognition
UART Control Character Recognition
Send Break
Send Preamble (IDLE)
Wakeup Timer
UART Error-Handling Procedure
UART Mode Register
UART Transmit Buffer Descriptor (Tx BD)
UART Event Register
UART Mask Register
S-Records Programming Example
Serial Interface Mask Register (SIMASK)
HDLC Controller
HDLC Channel Frame Transmission Processing
HDLC Channel Frame Reception Processing
HDLC Memory Map
HDLC Programming Model
HDLC Command Set
HDLC Address Recognition
HDLC Maximum Frame Length Register (MFLR)
HDLC Error-Handling Procedure
HDLC Mode Register
HDLC Receive Buffer Descriptor (Rx BD)
HDLC Transmit Buffer Descriptor (Tx BD)
HDLC Event Register
HDLC Mask Register
BISYNC Controller
BISYNC Channel Frame Reception Processing
BISYNC Command Set
BISYNC Control Character Recognition
BSYNC-BISYNC SYNC Register
BDLE-BISYNC OLE Register
BISYNC Mode Register
Bl SYNC Transmit Buffer Descriptor (Tx BO)
BISYNC Mask Register
DDCMP Controller
DDCMP Channel Frame Transmission Processing
DDCMP Channel Frame Reception Processing
DDCMP Memory Map
DDCMP Programming Model
DDCMP Command Set
DDCMP Control Character Recognition
DDCMP Address Recognition
DDCMP Error-Handling Procedure
DDCMP Mode Register
DDCMP Transmit Buffer Descriptor (Tx BD)
DDCMP Event Register
DDCMP Mask Register
Controller
Bit Rate Adaption of Synchronous Data Signaling Rates
Rate Adaption of 48- and 56-Kbps User Rates to 64 Kbps
Adaption for Asynchronous Rates up to 19.2 Kbps
Controller Overview
Programming Model
Error-Handling Procedure
Receive Buffer Descriptor (Rx BD)
Transmit Buffer Descriptor (Tx BD)
Event Register
Mask Register
Serial Communication Port (SCP)
SCP Programming Model
Serial Management Controllers (Smcs)
SCP Transmit/Receive Buffer Descriptor
SCP Transmit/Receive Processing
Overview
Using IDL with the Smcs
Using GCI with the Smcs
SMC Programming Model
SMC Memory Structure and Buffers Descriptors
SMC1 Receive Buffer Descriptor
SMC1 Transmit Buffer Descriptor
SMC2 Receive Buffer Descriptor
SMC2 Transmit Buffer Descriptor
SMC Interrupt Requests
Signal Description
Functional Groups
Power Pins
Clocks
System Control
Address Bus Pins A23-A 1
Bus Control Pins
Bus Arbitration Pins
Interrupt Control Pins
MC68302 Bus Interface Signal Summary
Physical Layer Serial Interface Pins
Nmsl1 or ISDN Interface Pins
Nmsl2 Port or Port a Pins
Nmsl3 Port or Port a Pins or SCP Pins
IDMA Pins or Port a Pins
IACK or PIO Port B Pins
Timer Pins
Parallel 1/0 Pins with Interrupt Capability
Chip-Select Pins
Maximum Ratings
Thermal Characteristics
Power Considerations
Power Dissipation
DC Electrical Characteristics
DC Electrical Characteristics - Nmsl1 in IDL Mode
Ac Electrical Specifications- Clock Timing
AC Electrical Specifications - IMP Bus Master Cycles
AC Electrical Specifications - External Master Internal Read/Write Cycles
AC Electrical Specifications - Internal Master Internal Read/Write Cycles
AC Electrical Specifications - Chip-Select Timing Internal Master
AC Electrical Specifications - Chip-Select Timing External Master
AC Electrical Specifications - Parallel 1/0
AC Electrical Specifications - Interrupts
Ac Electrical Specifications -Timers
AC Electrical Specifications - Serial Communication Port
AC Electrical Specifications - IDL Timing
AC Electrical Specifications - GCI Timing
AC Electrical Specifications - PCM Timing
AC Electrical Specifications - NMSI Timing
Pin Assignments
Pin Grid Array
Mechanical Data and Ordering Information
Ceramic Surface Mount (CQFP)
Package Dimensions
Ordering Information
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MC68302
Integrated
Multi-Protocol Processor
User's Manual
@MOTOROLA
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