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MC68302

User's Manual

Table of Contents

Summary of Contents for Motorola MC68302

Page 1 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.
Page 2 MC68302 USER’S MANUAL MOTOROLA...
Page 3 Processor Product Brief . The MC68302 Integrated Multiprotocol Processor User’s Manual describes the program- ming, capabilities, registers, and operation of the MC68302; the MC68000 Family Program- mer’s Reference Manual provides instruction details for the MC68302; and the MC68302 Low Power Integrated Multiprotocol Processor Product Brief provides a brief description of the MC68302 capabilities.
Page 4 JAPAN, Tachikawa 81(0425)23-6700 HYBRID COMPONENTS RESELLERS JAPAN, Tokyo 81(03)3440-3311 Elmo Semiconductor (818) 768-7400 JAPAN , Yokohama 81(045)472-2751 Minco Technology Labs Inc. (512) 834-2022 KOREA , Pusan 82(51)4635-035 Semi Dice Inc. (310) 594-4631 KOREA , Seoul 82(2)554-5188 MC68302 USER’S MANUAL MOTOROLA...
Page 5: Table Of Contents
Exception Vectors ................... 2-8 2.4.2 Exception Stacking Order ............... 2-9 Interrupt Processing ................2-11 M68000 Signal Differences ..............2-11 MC68302 IMP Configuration Control ............ 2-12 MC68302 Memory Map................. 2-14 Event Registers..................2-19 Section 3 System Integration Block (SIB) DMA Control.................... 3-2 3.1.1...
Page 6: Paragraph Title Page
Timer Capture Registers (TCR1, TCR2)..........3-39 3.5.2.4 Timer Counter (TCN1, TCN2)..............3-39 3.5.2.5 Timer Event Registers (TER1, TER2)............3-39 3.5.2.6 General Purpose Timer Example............3-40 3.5.2.6.1 Timer Example 1..................3-40 3.5.2.6.2 Timer Example 2..................3-40 3.5.3 Timer 3 - Software Watchdog Timer ............3-41 MC68302 USER’S MANUAL MOTOROLA...
Page 7 Command Set ..................4-5 4.3.1 Command Execution Latency ..............4-7 Serial Channels Physical Interface............4-7 4.4.1 IDL Interface..................4-11 4.4.2 GCI Interface ..................4-14 4.4.3 PCM Highway Mode................4-16 4.4.4 Nonmultiplexed Serial Interface (NMSI) ..........4-19 MOTOROLA MC68302 USER’S MANUAL...
Page 8 4.5.11.13 UART Mode Register................4-56 4.5.11.14 UART Receive Buffer Descriptor (Rx BD) ..........4-57 4.5.11.15 UART Transmit Buffer Descriptor (Tx BD)..........4-61 4.5.11.16 UART Event Register................4-63 4.5.11.17 UART MASK Register................4-65 4.5.11.18 S-Records Programming Example ............4-65 4.5.12 HDLC Controller..................4-66 viii MC68302 USER’S MANUAL MOTOROLA...
Page 9 DDCMP Transmit Buffer Descriptor (Tx BD)........4-112 4.5.14.12 DDCMP Event Register............... 4-114 4.5.14.13 DDCMP Mask Register ............... 4-115 4.5.15 V.110 Controller .................. 4-115 4.5.15.1 Bit Rate Adaption of Synchronous Data Signaling Rates up to 19.2 kbps..................4-116 MOTOROLA MC68302 USER’S MANUAL...
Page 10 SMC1 Transmit Buffer Descriptor ............4-142 4.7.4.3 SMC2 Receive Buffer Descriptor ............4-142 4.7.4.4 SMC2 Transmit Buffer Descriptor ............4-143 4.7.5 SMC Interrupt Requests ..............4-143 Section 5 Signal Description Functional Groups..................5-1 Power Pins....................5-2 Clocks ......................5-4 System Control ..................5-5 Address Bus Pins (A23–A1) ..............5-7 MC68302 USER’S MANUAL MOTOROLA...
Page 11 Data Bus Pins (D15—D0) ............... 5-7 Bus Control Pins..................5-8 Bus Arbitration Pins................5-10 Interrupt Control Pins ................5-11 5.10 MC68302 Bus Interface Signal Summary ..........5-12 5.11 Physical Layer Serial Interface Pins............5-13 5.12 Typical Serial Interface Pin Configurations ........... 5-14 5.13...
Page 12 D.1.3 Memory Interface ..................D-4 D.1.4 Memory Circuit..................D-4 D.1.5 Memory Timing Analysis................. D-4 Switching the External ROM and RAM Using the MC68302 ....D-5 D.2.1 Conditions at Reset................. D-5 D.2.2 First Things First ..................D-5 D.2.3 Switching Process................... D-6 MC68302 Buffer Processing and Interrupt Handling ......
Page 13 D.6.13 Additional IMP To S/T Chip Connections ..........D-39 D.6.14 Initialization of the MC145475 ...............D-40 D.6.15 MC145554 CODEC Filter..............D-41 Interfacing a Master MC68302 to One or More Slave MC68302s ..D-41 D.7.1 Synchronous vs. Asynchronous Accesses..........D-43 D.7.2 Clocking....................D-43 D.7.3 Programming the Base Address Registers (BARs).......D-43 D.7.4...
Page 14 Synchronous UART................D-67 D.8.13 SCP as a Transparent Mode Alternative ..........D-68 D.8.14 Transparent Mode Summary ..............D-68 An Appletalk Node with the MC68302 and MC68195 ......D-69 D.9.1 Overview of the Board ................D-70 D.9.2 Important Side Notes ................D-70...
Page 15 PAREC—Receive Parity Error Counter..........E-24 E.2.1.3.6 FRMEC—Receive Framing Error Counter..........E-24 E.2.1.3.7 NOSEC—Receive Noise Counter............E-24 E.2.1.3.8 BRKEC—Receive Break Condition Counter......... E-24 E.2.1.3.9 UADDR1 and UADDR2................. E-24 E.2.1.4 Receive Buffer Descriptors..............E-25 E.2.1.4.1 Receive BD Control/Status Word............E-26 MOTOROLA MC68302 USER’S MANUAL...
Page 16 Programming the SCC for Transparent ..........E-40 E.3.2.1 CP Initialization ..................E-40 E.3.2.2 General and Transparent Protocol-Specific RAM Initialization ..... E-41 E.3.2.3 SCC Initialization................... E-41 E.3.2.4 SCC Operation..................E-41 E.3.2.5 SCC Interrupt Handling................. E-41 Appendix F Design Checklist MC68302 USER’S MANUAL MOTOROLA...
Page 17 Figure 2-3. M68000 Bus/Address Error Exception Stack Frame........ 2-10 Figure 2-4. M68000 Short-Form Exception Stack Frame ........... 2-10 Figure 2-5. MC68302 IMP Configuration Control ............2-12 Section 3 System Integration Block (SIB) Figure 3-1. IDMA Controller Block Diagram ..............3-3 Figure 3-2.
Page 18 Figure 4-42. Transparent Receive Buffer Descriptor..........4-130 Figure 4-43. Transparent Transmit Buffer Descriptor..........4-131 Figure 4-44. SCP Timing .................... 4-135 Figure 4-45. SCP vs. SCC Pin Multiplexing ............... 4-137 Section 5 Signal Description Figure 5-1. Functional Signal Groups................5-3 xviii MC68302 USER’S MANUAL MOTOROLA...
Page 19 Figure 6-20. IDL Timing Diagram ................. 6-31 Figure 6-21. GCI Timing Diagram................. 6-33 Figure 6-22. PCM Timing Diagram (SYNC Envelopes Data) ........6-35 Figure 6-23. PCM Timing Diagram (SYNC Prior to 8-Bit Data) ........6-35 Figure 6-24. NMSI Timing Diagram ................6-37 MOTOROLA MC68302 USER’S MANUAL...
Page 20 Figure C-1. CP Architecture Running RAM Microcode ..........C-1 Appendix D MC68302 Applications Figure D-1. MC68302 Minimum System Configuration (Sheet 1 of 2)......D-2 Figure D-2. MC68302 Minimum System Configuration (Sheet 2 of 2)......D-3 Figure D-3. Transmit and Receive BD Structure............D-7 Figure D-4.
Page 21 Table 4-6. SCC Parameter RAM Memory Map............4-35 Table 4-7. UART Specific Parameter RAM..............4-46 Table 4-8. HDLC-Specific Parameter RAM..............4-69 Table 4-9. BISYNC Specific Parameter RAM ..............4-86 Table 4-10. DDCMP Specific Parameter RAM ............4-104 Table 4-11. Transparent-Specific Parameter RAM ............4-125 MOTOROLA MC68302 USER’S MANUAL...
Page 22: Table Title Page
Descriptors for SCCx ................E-31 Table E-3 (b). Transparent Programming Model (Continued) General Parameter and Transparent Protocol-Specific RAM for SCCx ......E-31 Table E-3 (c). SCCx Register Set ................E-32 Table E-3 (d). General Registers (Only One Set) ............E-32 xxii MC68302 USER’S MANUAL MOTOROLA...
Page 23: General Description
SECTION 1 GENERAL DESCRIPTION The MC68302 integrated multiprotocol processor (IMP) is a very large-scale integration (VL- SI) device incorporating the main building blocks needed for the design of a wide variety of controllers. The device is especially suitable to applications in the communications industry.
Page 24: General Description
PARALLEL I/O REFRESH CONTROLLER SYSTEM INTEGRATION BLOCK PERIPHERAL BUS 6 CHANNELS SDMA SMC (2) SCC1 SCC2 SCC3 MAIN CONTROLLER (RISC) SERIAL CHANNELS PHYSICAL INTERFACE COMMUNICATIONS PROCESSOR I/O PORTS AND PIN ASSIGNMENTS Figure 1-1. MC68302 Block Diagram MC68302 USER’S MANUAL MOTOROLA...
Page 25: Features
General Description The MC68302 can also be used in applications such as board-level industrial controllers performing real-time control applications with a local control bus and an X.25 packet network connection. Such a system provides the real-time response to a demanding peripheral while permitting remote monitoring and communication through an X.25 packet network.
Page 26: Mc68302 System Architecture
CHANNELS Figure 1-2. General-Purpose Microprocessor System Design The MC68302 microprocessor architecture is shown in Figure 1-3. In this architecture, the peripheral devices are isolated from the system bus through a dual-port memory. Various parameters and counters and all memory buffer descriptor tables reside in the dual-port RAM.
Page 27: Nmsi Communications-Oriented Environment
The net effect is the loss of a single memory access by the CP main controller per M68000 core access. The buffer memory structure of the MC68302 can be configured to closely match I/O chan- nel requirements by careful selection of buffer size and buffer linking. The interrupt structure...
Page 28: Basic Rate Isdn Or Digital Voice/Data Terminal
A basic rate ISDN (2B + D) or digital voice/data terminal can be made from a chip set based on the MC68302. Refer to Figure 1-5 for an example of a basic rate ISDN voice/data termi- nal. In this terminal, the CP can directly support the 2B + D channels and perform either V.110 or V.120 rate adaption.
Page 29: Figure 1-4. Nmsi Communications-Oriented Board Design
General Description Figure 1-4. NMSI Communications-Oriented Board Design MOTOROLA MC68302 USER’S MANUAL...
Page 30: Figure 1-5. Basic Rate Idl Voice/Data Terminal In Isdn
General Description Figure 1-5. Basic Rate IDL Voice/Data Terminal in ISDN MC68302 USER’S MANUAL MOTOROLA...
Page 31: Mc68000/Mc68008 Core
Integrated Services Digital Network (ISDN). The MC68302 can operate either in the full MC68000 mode with a 16-bit data bus or in the MC68008 mode with an 8-bit data bus by tying the bus width (BUSW) pin low. UDS/A0 func- tions as A0 and LDS/DS functions as DS in the MC68008 mode.
Page 32: Mc68000/Mc68008 Core
(eight levels available) as well as the following condition codes: overflow (V), zero (Z), negative (N), carry (C), and extend (X). Additional status bits indicate that the processor is in trace (T) mode and/or in a supervisor (S) state. MC68302 USER’S MANUAL MOTOROLA...
Page 33: Instruction Set Summary
Figure 2-2. M68000 Status Register 2.2 INSTRUCTION SET SUMMARY The five data types supported by the M68000 on the MC68302 are bits, binary-coded deci- mal (BCD) digits (4 bits), bytes (8 bits), words (16 bits), and long words (32 bits).
Page 34: Table 2-1. M68000 Data Addressing Modes
1 for byte, 2 for word, and 4 for long word. If An is the stack pointer and the operand size is byte, N = 2 to keep the stack pointer on a word boundary. Replaces MC68302 USER’S MANUAL MOTOROLA...
Page 35: Table 2-2. M68000 Instruction Set Summary
STOP Stop Jump to Subroutine Subtract SWAP Swap Data Register Halves Load Effective Address Test and Set Operand LINK Link Stack TRAP Trap Logical Shift Left TRAPV Trap on Overflow Logical Shift Right Test UNLK Unlink MOTOROLA MC68302 USER’S MANUAL...
Page 36: Address Spaces
In the M68000 Family, the address spaces are indicated by function code pins. On the M68000, three function code pins are output from the device on every bus cycle of every executed instruction. This provides the purpose of each bus cycle to external logic. MC68302 USER’S MANUAL MOTOROLA...
Page 37: Table 2-4. M68000 Address Spaces
On the MC68302, this capability is provided for each potential internal bus master (i.e., the IDMA, SDMA, and DRAM refresh units). Also on the MC68302, provision is made for the decoding of function codes that are output from external bus masters (e.g., in the chip-select generation logic).
Page 38: Exception Processing
Table 2-5. M68000 Exception Vector Assignment Vector Address Decimal Space Assignment Number Reset: Initial SSP Reset: Initial PC Bus Error Address Error Illegal Instruction Zero Divide CHK Instruction TRAPV Instruction Privilege Violation Trace Line 1010 Emulator MC68302 USER’S MANUAL MOTOROLA...
Page 39: Exception Stacking Order
NOTES: 1. Vector numbers 12–14, 16–23, and 48–63 are reserved for future enhancements by Motorola (with vectors 60–63 being used by the M68302 (see 2.7 MC68302 IMP Conﬁguration and Control)). No user peripheral devices should be assigned these numbers. 2. Unlike the other vectors which only require two words, reset vector (0) requires four words and is located in the supervisor program space.
Page 40: Figure 2-3. M68000 Bus/Address Error Exception Stack Frame
PROGRAM COUNTER HIGH PROGRAM COUNTER LOW Figure 2-4. M68000 Short-Form Exception Stack Frame NOTE The MC68302 uses the exact same exception stack frames as the MC68000. For exception processing times and instruction execution times, refer to MC68000UM/AD, 8-/16-/32-Bit Microprocessor User's Manual .
Page 41: Interrupt Processing
MC68000-core-initiated read-modify-write cycle. The MC68302 can be programmed to use the RMC signal to negate address strobe (AS) at the end of the read portion of the cycle and assert AS at the beginning of the write portion of the cycle (See 3.8.3 System Control Bits).
Page 42: Mc68302 Imp Configuration Control
3.8.1 System Control Register (SCR). The CKCR entry contains the CKCR reg- ister described in 3.9 Clock Control Register. Figure 2-5 shows all the MC68302 IMP on-chip addressable locations and how they are mapped into system memory. SYSTEM MEMORY MAP...
Page 43 4K-byte block of on-chip peripherals. The address compare logic uses these bits, dependent upon the CFC bit, to cause an address match within its address space. NOTE Do not assign this field to the M68000 core interrupt acknowl- edge space (FC2–FC0 = 7). MOTOROLA MC68302 USER’S MANUAL 2-13...
Page 44: Mc68302 Memory Map
The following tables show the additional registers added to the M68000 to make up the MC68302. All of the registers are memory-mapped. Four entries in the M68000 exception vectors table (located in low RAM) are reserved for addresses of system configuration reg- isters (see Table 2-6) that reside on-chip.
Page 45: Table 2-8. Parameter Ram
4.5 Serial Communication Controllers (SCCs). Base + 67E contains the MC68302 revi- sion number. Revision A parts (mask 1B14M) correspond to the value $0001. Revision B parts (mask 2B14M and 3B14M which are described in this manual) correspond to the value $0002.
Page 46 SMC1–SMC2 Internal Use Base +67A Word Rx/TxBD SCC1–SCC3 BERR Channel Number Base +67C Word Base +67E # Word MC68302 Revision Number Base + 680 SCC3 • • Specific Protocol Parameters • Base + 6BF SCC3 Base + 6C0 • Reserved •...
Page 47: Table 2-9. Internal Registers
Option Register 1 DFFD Base + 838 # Base Register 2 C000 Base + 83A # Option Register 2 DFFD Base + 83C # Base Register 3 C000 Option Register 3 DFFD Base + 83E # MOTOROLA MC68302 USER’S MANUAL 2-17...
Page 48 Base + 899 SCC2 Reserved Base + 89A SCCM2 SCC2 SCC2 Mask Register Base + 89B SCC2 Reserved Base + 89C SCCS2 SCC2 SCC2 Status Register Base + 89D SCC2 Reserved Base + 89E SCC2 2-18 MC68302 USER’S MANUAL MOTOROLA...
Page 49: Event Registers
(RST) bit located in a register in that block. This RST bit will reset that entire block, including any event registers contained therein. Examples: 1. To clear bit 0 of SCCE1, execute "MOVE.B #$01,SCCE1" MOTOROLA MC68302 USER’S MANUAL 2-19...
Page 50 Thus, if a bit is a one when read, it will be written back with a one, clearing that bit. For example, the in- struction “BSET.B #0,SCCE1” will actually clear ALL bits in SCCE1, not just bit 0. 2-20 MC68302 USER’S MANUAL MOTOROLA...
Page 51: System Integration Block (Sib)
SECTION 3 SYSTEM INTEGRATION BLOCK (SIB) The MC68302 contains an extensive SIB that simplifies the job of both the hardware and software designer. It integrates the M68000 core with the most common peripherals used in an M68000-based system. The independent direct memory access (IDMA) controller re- lieves the hardware designer of the extra effort and board logic needed to connect an exter- nal DMA controller.
Page 52: Dma Control
Note that the chip se- lect and wait state generation logic on the MC68302 may be used with the IDMA, if desired. Every IDMA cycle requires between two and four bus cycles, depending on the address boundary and transfer size.
Page 53: Idma Registers (Independent Dma Controller)
Figure 3-1. IDMA Controller Block Diagram 3.1.2 IDMA Registers (Independent DMA Controller) The IDMA has six registers that define its specific operation. These registers include a 32- bit source address pointer register (SAPR), a 32-bit destination address pointer register MOTOROLA MC68302 USER’S MANUAL...
Page 54: Channel Mode Register (Cmr)
1 = If a bus error occurs during an operand transfer either on BES or BED, the channel generates an interrupt to the IMP interrupt controller and sets the appropriate bit (BES or BED) in the CSR. MC68302 USER’S MANUAL MOTOROLA...
Page 55 00 = IDMA gets up to 75% of the bus bandwidth. 01 = IDMA gets up to 50% of the bus bandwidth. 10 = IDMA gets up to 25% of the bus bandwidth. 11 = IDMA gets up to 12.5% of the bus bandwidth. MOTOROLA MC68302 USER’S MANUAL...
Page 56: Source Address Pointer Register (Sapr)
$00000000. This register can be incremented by one or two, depending on the SSIZE bit and the starting address in this register. 3.1.2.3 Destination Address Pointer Register (DAPR) The DAPR is a 32-bit register. RESERVED DESTINATION ADDRESS POINTER MC68302 USER’S MANUAL MOTOROLA...
Page 57: Function Code Register (Fcr)
A bit is cleared by writing a one and is left unchanged by writing a zero. More than one bit may be cleared at a time, and the register is cleared at reset. RESERVED DONE Bits 7–4—These bits are reserved for future use. MOTOROLA MC68302 USER’S MANUAL...
Page 58: Interface Signals
DONE may be used as an input to the IDMA controller indicating that the device being serviced requires no more transfers and that the transmission is to be ter- minated. DONE is an output if the transfer count is exhausted. MC68302 USER’S MANUAL MOTOROLA...
Page 59: Idma Operational Description
When the complete operand is written, the DAPR is incremented by one or two, and the BCR is decremented by the number of bytes transferred. See 3.1.2.3 Desti- nation Address Pointer Register (DAPR) and 3.1.2.5 Byte Count Register (BCR) for more details. MOTOROLA MC68302 USER’S MANUAL...
Page 60: Address Sequencing
16 Bit Byte Word Operand Packing Read Word—Write Byte, Write Byte 16 Bit Word Byte Operand Unpacking 16 Bit Word Word Read Word—Write Word Refer toTable 3-2 for more details on the IDMA bus cycles. 3-10 MC68302 USER’S MANUAL MOTOROLA...
Page 61: Transfer Request Generation
External Burst Mode For external devices requiring very high data transfer rates, the external burst mode al- lows the IDMA to use all the bus bandwidth to service the device. In the burst mode, the MOTOROLA MC68302 USER’S MANUAL 3-11...
Page 62: Block Transfer Termination
STR is cleared, and an interrupt is generated if INTN is set. The SAPR and/or DAPR are also incremented in the normal fashion. NOTE If the channel is started with BCR value set to zero, the channel will transfer 64K bytes. 3-12 MC68302 USER’S MANUAL MOTOROLA...
Page 63: Idma Programming
IDMA status changes, status bits are set in the CSR but not in the IPR. When either INTN or INTE is set and the corresponding event occurs, the appropriate bit is set in the IPR, and, if this bit is not masked, the interrupt controller will interrupt the M68000 core. MOTOROLA MC68302 USER’S MANUAL 3-13...
Page 64: Dma Bus Arbitration
M68000 core: reset, bus error, halt, and retry. NOTE These exceptions also apply to the SDMA channels except that the bus error reporting method is different. See 4.5.8.4 Bus Error on SDMA Access for further details. 3-14 MC68302 USER’S MANUAL MOTOROLA...
Page 65: Reset
• Two Operational Modes: Normal and Dedicated • Eighteen Prioritized Interrupt Sources (Internal and External) • A Fully Nested Interrupt Environment • Unique Vector Number for Each Internal/External Source Generated • Three Interrupt Request and Interrupt Acknowledge Pairs MOTOROLA MC68302 USER’S MANUAL 3-15...
Page 66: Overview
1. The interrupt controller on the IMP collects interrupt events from on and off-chip pe- ripherals, prioritizes them, and presents the highest priority request to the M68000 core. 2. The M68000 responds to the interrupt request by executing an interrupt acknowledge 3-16 MC68302 USER’S MANUAL MOTOROLA...
Page 67: Interrupt Controller Overview
In this mode, the three external interrupt request pins are configured as IPL2–IPL0 as in the original MC68000. Up to seven levels of interrupt priority may be encoded. Level 4 is reserved for IMP INRQ interrupts and may not be generated by an external device. MOTOROLA MC68302 USER’S MANUAL 3-17...
Page 68: Interrupt Priorities
INRQ interrupts are assigned to level 4 (fixed). EXRQ interrupts are assigned by the user to any of the remaining six priority levels in normal mode. In dedi- cated mode, EXRQ interrupts may be assigned to priority levels 7, 6, and 1. 3-18 MC68302 USER’S MANUAL MOTOROLA...
Page 69: Inrq Interrupt Source Priorities
M68000 core for servicing. After the vector number corresponding to this interrupt is passed to the core during an interrupt acknowledge cycle, an INRQ interrupt request is cleared in IPR. (EXRQ requests must be cleared externally.) The remaining interrupt MOTOROLA MC68302 USER’S MANUAL 3-19...
Page 70: Masking Interrupt Sources And Events
By clearing all unmasked bits in the event register, the IPR bit is also cleared. 3-20 MC68302 USER’S MANUAL MOTOROLA...
Page 71: Interrupt Vector
The IMP can generate vectors for up to seven external peripherals by connecting the exter- nal request lines to IRQ7, IRQ6, IRQ1, PB11, PB10, PB9, and PB8. PB11, PB10, PB9, and PB8 are prioritized within level 4. MOTOROLA MC68302 USER’S MANUAL 3-21...
Page 72 3-4. When the core initiates an interrupt acknowledge cycle for level 4 and there is no internal interrupt pending, the interrupt controller encodes the error code 00000 onto the five low-order bits of the interrupt vector. 3-22 MC68302 USER’S MANUAL MOTOROLA...
Page 73: Figure 3-4. Scc1 Vector Calculation Example
PURPOSELY CHOSEN TO CAUSE THIS. 3. READ 32-BIT VALUE AT $2B4 AND JUMP INTERRUPT HANDLER BEGINS AT $2B4 0007 $070302 (24-BIT ADDRESSES ARE USED $2B6 0302 ON THE M68000). Figure 3-4. SCC1 Vector Calculation Example MOTOROLA MC68302 USER’S MANUAL 3-23...
Page 74: Interrupt Controller Programming Model
0 = Internal vector. The interrupt controller will provide the vector number for a level 1 interrupt acknowledge cycle. 1 = External vector. The interrupt controller will not provide the vector number for a lev- el 1 interrupt. 3-24 MC68302 USER’S MANUAL MOTOROLA...
Page 75 IOUT2–IOUT0 to another pro- cessor (MC68302, MC68020, etc.) For cases when the slave MC68302 does not generate a level 4 vector (i.e., the VGE bit is cleared), one must set the ET1, ET6, and ET7 bits to level-trig- gered and then negate the IRQ1, IRQ6, and IRQ7 lines external- ly in the interrupt handler code.
Page 76: Interrupt Pending Register (Ipr)
The ERR bit is set if the user drives the IPL2–IPL0 lines to inter- rupt level 4 and no INRQ interrupt is pending. PB11 PB10 SCC1 SDMA IDMA SCC2 TIMER1 SCC3 TIMER2 TIMER3 SMC1 SMC2 3-26 MC68302 USER’S MANUAL MOTOROLA...
Page 77: Interrupt Mask Register (Imr)
To clear bits that were set by multiple interrupt events, the user should clear all the unmasked events in the corresponding on- chip peripheral's event register. PB11 PB10 SCC1 SDMA IDMA SCC2 TIMER1 SCC3 TIMER2 TIMER3 SMC1 SMC2 — MOTOROLA MC68302 USER’S MANUAL 3-27...
Page 78: Interrupt In-Service Register (Isr)
Example 1—Timer 3 (Software Watchdog Timer) Interrupt Handler 1. Vector to interrupt handler. 2. (Handle Event) 3. Clear the TIMER3 bit in the ISR. 4. Execute RTE instruction. Example 2— SCC1 Interrupt Handler 1. Vector to interrupt handler. 3-28 MC68302 USER’S MANUAL MOTOROLA...
Page 79: Parallel I/O Ports
A control register (PACNT) bit is cleared. Port A pins are configured as dedicated on-chip peripheral pins if the corresponding PACNT bit is set. An example block diagram of PA0 is given in Figure 3-5 MOTOROLA MC68302 USER’S MANUAL 3-29...
Page 80: Figure 3-5. Parallel I/O Block Diagram For Pa0
SCC2 to operate in a nonmultiplexed mode without the modem control lines and exter- nal clocks (RCLK2, TCLK2, CD2, CTS2, and RTS2) may dedicate the data lines (RXD2 and TXD2) to SCC2 and configure the others as general-purpose I/O pins. What the peripheral 3-30 MC68302 USER’S MANUAL MOTOROLA...
Page 81: Port B
PB7–PB0 functions exactly like PA15–PA0, except that PB7–PB0 is controlled by the port B control register (PBCNT), the port B data direction register (PBDDR), and the port B data register (PBDAT), and PB7 is configured as an open-drain output (WDOG) upon total system reset. MOTOROLA MC68302 USER’S MANUAL 3-31...
Page 82: Pb11-Pb8
The I/O port consists of three memory-mapped read-write 16-bit registers for port A and three memory-mapped read-write 16-bit registers for port B. Refer to Figure 3-6 for the I/O port registers. The reserved bits are read as zeros. 3-32 MC68302 USER’S MANUAL MOTOROLA...
Page 83: Dual-Port Ram
The CP has 1152 bytes of static RAM configured as a dual-port memory. The dual-port RAM can be accessed by the CP main controller or by one of three bus masters: the M68000 core, the IDMA, or an external master. The M68000 core and the IDMA access the RAM synchro- MOTOROLA MC68302 USER’S MANUAL 3-33...
Page 84 As CP microcode RAM, it is used exclusively to store microcode for the CP main con- troller, allowing the development of special protocols or protocol enhancements, under spe- cial arrangement with Motorola. Appendix C discusses available offerings. The RAM block diagram is shown in Figure 3-7. The M68000 core, the IDMA, and the ex- ternal master access the RAM through the IMP bus interface unit (BIU) using the M68000 bus.
Page 85: Timers
ADDRESS Figure 3-7. RAM Block Diagram 3.5 TIMERS The MC68302 includes three timer units: two identical general-purpose timers and a soft- ware watchdog timer. Each general-purpose timer consists of a timer mode register (TMR), a timer capture regis- ter (TCR), a timer counter (TCN), a timer reference register (TRR), and a timer event register (TER).
Page 86: Timer Key Features
• Programmable Sources for the Clock Input • Input Capture Capability • Output Compare with Programmable Mode for the Output Pin • Two Timers Cascadable to Form a 32-Bit Timer • Free Run and Restart Modes 3-36 MC68302 USER’S MANUAL MOTOROLA...
Page 87: General Purpose Timer Units
The timer registers may be modified at any time by the user. 3.5.2.1 Timer Mode Register (TMR1, TMR2) TMR1 and TMR2 are identical 16-bit registers. TMR1 and TMR2, which are memory- mapped read-write registers to the user, are cleared by reset. PRESCALER VALUE (PS) ICLK MOTOROLA MC68302 USER’S MANUAL 3-37...
Page 88: Timer Reference Registers (Trr1, Trr2)
(see 3.5.2.6 General Purpose Timer Example). 3.5.2.2 Timer Reference Registers (TRR1, TRR2) Each TRR is a 16-bit register containing the reference value for the timeout. TRR1 and TRR2 are memory-mapped read-write registers. 3-38 MC68302 USER’S MANUAL MOTOROLA...
Page 89: Timer Capture Registers (Tcr1, Tcr2)
INRQ to the interrupt controller. This register is cleared at reset. RESERVED CAP—Capture Event The counter value has been latched into the TCR. The CE bits in the TMR are used to enable the interrupt request caused by this event. MOTOROLA MC68302 USER’S MANUAL 3-39...
Page 90: General Purpose Timer Example
1. Program the Port B control register to change the port pin from a general purpose input pin to TOUT. 2. Program the TRR to $61A8 ( = 50000/2). 3. Program the TMR to $321B (prescaler = 3, OM =1 to toggle TOUT, FRR = 1 to restart 3-40 MC68302 USER’S MANUAL MOTOROLA...
Page 91: Timer 3 - Software Watchdog Timer
Reset initializes the register to $FFFF, enabling the watchdog timer and setting it to the max- imum timeout period. This causes a timeout to occur if there is an error in the boot program. MOTOROLA MC68302 USER’S MANUAL 3-41...
Page 92: Software Watchdog Counter (Wcn)
3.6 EXTERNAL CHIP-SELECT SIGNALS AND WAIT-STATE LOGIC The MC68302 provides a set of four programmable chip-select signals. Each chip-select signal has an identical internal structure. For each memory area, the user may also define an internally generated cycle termination signal (DTACK).
Page 93 A priority structure exists within the chip-select block. For a given address, the priority is as follows: 1. Access to any IMP internal address (BAR, dual-port RAM, etc.) No chip select asserted. 2. Chip Select 0 3. Chip Select 1 4. Chip Select 2 5. Chip Select 3 MOTOROLA MC68302 USER’S MANUAL 3-43...
Page 94: Figure 3-9. Chip-Select Block Diagram
(WPVE) is set. The CS line will not be asserted. NOTE The chip-select logic is reset only on total system reset (asser- tion of RESET and HALT). Accesses to the internal RAM and registers, including the system configuration registers (BAR and 3-44 MC68302 USER’S MANUAL MOTOROLA...
Page 95: Chip-Select Logic Key Features
FC2–FC0 —Function Code Field This field is contained in bits 15–13 of each BR. These bits are used to set the address space function code. The address compare logic uses these bits to determine whether an MOTOROLA MC68302 USER’S MANUAL 3-45...
Page 96 On write protect violation cycles (RW = 0 and MRW = 1), BERR will be generated if WPVE is set, and WPV will be set. If the write protect mechanism is used by an external master, the R/W low to AS asserted timing should be 16 ns minimum. 3-46 MC68302 USER’S MANUAL MOTOROLA...
Page 97: Option Registers (Or3-Or0)
The CS lines are asserted slightly earlier for internal IMP master memory cycles than for an external master using the CS lines. Set external master wait state (EMWS) in the SCR whenever these timing differences require an extra memory wait state for external masters. MOTOROLA MC68302 USER’S MANUAL 3-47...
Page 98: Chip Select Example
Set up chip select 2 to assert for a 1 Megabyte block of external RAM beginning at $200000 with 1 wait state. Note that the address must be on a block boundary (i.e. the starting ad- dress of a 1 Megabyte block could not be $210000). 3-48 MC68302 USER’S MANUAL MOTOROLA...
Page 99: On-Chip Clock Generator
(C L ) of this circuit is 20 pF, calculated as (C1 + C in )/2, where C1 = C2 = 25 pF and C in = 15 pF maximum on the EXTAL pin. MC68302 EXTAL XTAL Figure 3-10. Using an External Crystal MOTOROLA MC68302 USER’S MANUAL 3-49...
Page 100: System Control
The SCR is a memory-mapped read-write register. The address of this register is fixed at $0F4 in supervisor data space (FC = 5). ERRE WPVE RMCST EMWS ADCE BCLM FRZW FRZ2 FRZ1 HWDEN HWDCN2–HWDCN0 LPREC LPP16 LPEN LOW-POWER CLOCK DIVIDER Figure 3-11. System Control Register 3-50 MC68302 USER’S MANUAL MOTOROLA...
Page 101: System Status Bits
In the case of nested interrupts, the user may wish to clear the IPA bit only at the end of the original lower priority interrupt rou- tine to keep BCLR asserted until it completes. To guarantee that MOTOROLA MC68302 USER’S MANUAL 3-51...
Page 102: System Control Bits
WPVE—Write Protect Violation Enable 0 = BERR is not asserted when a write protect violation occurs. 1 = BERR is asserted when a write protect violation occurs. After system reset, this bit defaults to zero. 3-52 MC68302 USER’S MANUAL MOTOROLA...
Page 103 1 = The MC68302 uses RMC to negate AS and CS at the end of the read portion of the RMC cycle and reasserts AS and CS at the beginning of the write portion. BG will not be asserted until the end of the write portion.
Page 104: Disable Cpu Logic (M68000)
MC68302. In applications such as disable CPU mode, in which the M68000 core is not operating, the user should note that SAM may be changed by an external master on the first access of the MC68302, but that first write access must be asynchronous with three wait states.
Page 105 2. BG will be an input to the IDMA and SDMA from the external M68000 bus, rather than being an output from the MC68302. When BG is sampled as low by the MC68302, it waits for AS, BERR, HALT, and BGACK to be negated, and then asserts BGACK and performs one or more bus cycles.
Page 106: Bus Arbitration Logic
IDMA channels do not affect BR and BG, but only BGACK (unless disable CPU mode is used). The MC68302 provides several options for changing the preceding bus master priority list. The options are configured by setting the BCLM bit in the SCR and deciding whether or not the BCLR pin is used externally to cause external bus masters to relinquish the bus (see Table 3-10).
Page 107: Figure 3-12. Imp Bus Arbiter
ER + CG IR & CG EXTERNAL BUS REQUEST INTERNAL BUS REQUEST (IDMA OR SDMA) CORE BUS GRANT EXTERNAL GRANT INTERNAL GRANT ER & CG IDLE BUS IDLE OR CORE CYCLE Figure 3-12. IMP Bus Arbiter MOTOROLA MC68302 USER’S MANUAL 3-57...
Page 108: External Bus Arbitration
An external bus master may gain ownership of the M68000 bus by asserting the bus request (BR) pin. After gaining ownership, it may access the IMP registers or RAM or any system memory address. Chip selects and system control functions, such as the hardware watch- dog, continue to operate. 3-58 MC68302 USER’S MANUAL MOTOROLA...
Page 109: Hardware Watchdog
The hardware watchdog logic uses four bits in the SCR. HWDEN—Hardware Watchdog Enable 0 = The hardware watchdog is disabled. 1 = The hardware watchdog is enabled. After system reset, this bit defaults to one to enable the hardware watchdog. MOTOROLA MC68302 USER’S MANUAL 3-59...
Page 110: Reducing Power Consumption
M68000 core and when it is desirable to reduce system power consumption to its minimum value. All low-power modes are entered by first setting the low-power enable (LPEN) bit, and then executing the M68000 STOP in- struction. 3-60 MC68302 USER’S MANUAL MOTOROLA...
Page 111: Low-Power Mode
5. When a timer 1 or 2 interrupt occurs, the M68000 resumes execution with the timer 1 or 2 interrupt handler. After the RTE instruction, execution continues with the instruc- tion following the STOP instruction in step 4 above. All IMP state information is re- tained. MOTOROLA MC68302 USER’S MANUAL 3-61...
Page 112: Lowest Power Mode
NOTE The use of external clocks with the SCCs allows the original se- rial rates to be maintained; however, before attempting this, the SCC performance data should be carefully reviewed (see Ap- 3-62 MC68302 USER’S MANUAL MOTOROLA...
Page 113 LPCD0 0 to 31) can be selected. After a system reset, these bits default to zero. LPEN—Low-power Enable 0 = The low-power modes are disabled. 1 = The low-power modes are enabled. After a system reset, this bit defaults to zero to disable the low-power modes. MOTOROLA MC68302 USER’S MANUAL 3-63...
Page 114: Clock Control Register
TCLK1. This option may also be chosen if it is re- quired to run the SCC1 baud rate generator at high speed (for instance in a high speed UART application), but the TCLK1 output is not needed, and it is desired to 3-64 MC68302 USER’S MANUAL MOTOROLA...
Page 115: Freeze Control
Although DBRG1 may be modified at any time, the user should note that glitches on BRG1 are not prevented by the MC68302 when the state of DBRG1 is changed. Bits 10 - 0—Reserved. Should be written with zeros.
Page 116: Dynamic Ram Refresh Controller
RAM (DRAM) refresh task without any intervention from the M68000 core. Use of this feature requires a timer or SCC baud rate generator (either from the MC68302 or ex- ternally), the I/O pin PB8, and two transmit buffer descriptors from SCC2 (Tx BD6 and Tx BD7).
Page 117: Dram Refresh Controller Bus Timing
The refresh operation is a byte read operation. Thus, UDS or LDS will be asserted from the MC68302, but not both. A refresh to an odd address will assert LDS; whereas, a refresh to an even address will assert UDS.
Page 118: Initialization
RAM starting address. This param- eter should be initialized by the user before activating the refresh routine. NOTE The FC bits should not be programmed to the value “111.” 3-68 MC68302 USER’S MANUAL MOTOROLA...
Page 119: Programming Example
IMP. Depending on the PAL design, an increment value of $0002 can actually refresh a word at a time, even though the refresh access from the MC68302 is a byte read. The COUNT value is the number of word refreshes required in the entire DRAM bank.
Page 120 System Integration Block (SIB) 3-70 MC68302 USER’S MANUAL MOTOROLA...
Page 121: Communications Processor (Cp)
• Six Serial Direct Memory Access (SDMA) Channels • A Command Set Register • Serial Channels Physical Interface Including: —Motorola Interchip Digital Link (IDL) —General Circuit Interface (GCI), also known as IOM-2 —Pulse Code Modulation (PCM) Highway Interface —Nonmultiplexed Serial Interface (NMSI) Implementing Standard —Modem Signals...
Page 122: Figure 4-1. Simplified Cp Architecture
The main controller has a priority scheduler that determines which microcode routine is called when more than one internal request is pending. Requests are serviced in the follow- ing priority: 1. CP or System Reset 2. SDMA Bus Error MC68302 USER’S MANUAL MOTOROLA...
Page 123: Sdma Channels
RAM as shown in path 1. In path 2, data is sent over the peripheral bus to the in- ternal dual-port RAM. The SMCs and SCP, shown in path 3, always route their data to the dual-port RAM since they only receive and transmit a byte at a time. MOTOROLA MC68302 USER’S MANUAL...
Page 124: Figure 4-2. Three Serial Data Flow Paths
HDLC or transparent protocols where it writes 16 bits at a time. Each bus cycle is a standard M68000-type bus cycle. The chip select and wait state generation logic on the MC68302 may be used with the SDMA channels. NOTE...
Page 125: Command Set
For instance, BCLR can be connected through logic to the external master's HALT signal, and then be negated exter- nally when the external master's AS signal is negated. BCLR as seen from the MC68302 is negated by the SDMA during its access to memory.
Page 126 CH. NUM.—Channel Number These bits are set by the M68000 core to define the specific SCC channel that the com- mand is to operate upon. 00 = SCC1 01 = SCC2 10 = SCC3 11 = Reserved MC68302 USER’S MANUAL MOTOROLA...
Page 127: Command Execution Latency
3. IDL—Interchip Digital Link 4. GCI—General Circuit Interface The most generic physical interface on the MC68302 is the nonmultiplexed serial interface (NMSI). The NMSI consists of seven of the basic modem (or RS-232) signals: TXD, TCLK, RXD, RCLK, RTS, CTS, and CD. Each SCC can have its own set of NMSI signals as shown in Figure 4-3.
Page 128: Figure 4-3. Nmsi Physical Interface
I/O. If a multiplexed mode is chosen, the baud rate gen- erator clock is output on the BRG or TCLK pin, depending on whether the NMSI mode or multiplexed mode, respectively, was chosen for that SCC. MC68302 USER’S MANUAL MOTOROLA...
Page 129: Figure 4-4. Multiplexed Mode On Scc1 Opens Additional Configuration Possibilities
NOTE: MUX is deﬁned as one of the following: IDL, GCI, or PCM highway. The PCM highway interface is a flexible time-division multiplexed interface. It allows the MC68302 to connect to popular time-slot interfaces such as T1 and CEPT as well as user- defined time-slot interfaces.
Page 130: Figure 4-5. Serial Channels Physical Interface Block Diagram
When using the IDL or GCI buses, additional control functions in the frame structure are re- quired. These functions are supported in the MC68302 through two SMC channels: SMC1 and SMC2. (For other matters relating to the SMCs, refer to 4.7 Serial Management Con- trollers (SMCs)).
Page 131: Idl Interface
The IDL interface is a full-duplex ISDN interface used to interconnect a physical layer device (such as the Motorola ISDN S/T transceiver MC145474) to the integrated multiprotocol pro- cessor (IMP). Data on five channels (B1, B2, D, A, and M) is transferred in a 20-bit frame every 125 s, providing 160-kbps full-duplex bandwidth.
Page 132: Figure 4-7. Idl Terminal Adaptor
B1 and B2 channels. These signals are used for interfacing devices that do not support the IDL bus. These signals, configured by the SIMASK register, are active only for bits that are not masked. The IDL signals are as follows: 4-12 MC68302 USER’S MANUAL MOTOROLA...
Page 133 D channel. If a collision is detected on the D channel, the physical layer device ne- gates L1GR. The IMP then stops its transmission and retransmits the frame when L1GR is asserted again. This is handled automatically for the first two buffers of the frame. MOTOROLA MC68302 USER’S MANUAL 4-13...
Page 134: Gci Interface
B1 and B2 channels and the data rate clock (L1CLK). These signals are used for interfacing devices that do not support the GCI bus. They are configured with the SIMASK register and are active only for bits that are not masked. 4-14 MC68302 USER’S MANUAL MOTOROLA...
Page 135: Figure 4-8. Gci Bus Signals
64-kbps Monitor Channel (8 bits) 16-kbps Signaling Channel (2 bits) C/I, A, E 48-kbps Command/Indication Channel (6 bits) In addition to the 144-kbps ISDN 2B + D channels, GCI provides two channels for mainte- nance and control functions. MOTOROLA MC68302 USER’S MANUAL 4-15...
Page 136: Pcm Highway Mode
In PCM highway mode, one, two, or all three SCCs can be multiplexed together to support various time-division multiplexed interfaces. PCM highway supports the standard T1 and CEPT interfaces as well as user-defined interfaces. In this mode, the NMSI1 pins have new names and functions (see Table 4-2). 4-16 MC68302 USER’S MANUAL MOTOROLA...
Page 137: Table 4-2. Pcm Highway Mode Pin Functions
Three Request-to-Send Signals Outputs L1CLK is always an input to the MC68302 in PCM highway mode and is used as both a re- ceive and transmit clock. Thus, data is transmitted and received simultaneously in PCM highway mode. (If receive data needs to be clocked into the MC68302 at a different time or speed than transmit data is being clocked out, then NMSI mode should be used instead of PCM highway.)
Page 138: Figure 4-9. Two Pcm Sync Methods
RTS signals are not needed, they can be ignored or reassigned as parallel I/O. 1 CLOCK CYCLE SYNC PRIOR L1SY0 L1SY1 8-BIT ENVELOPE L1SY0 L1SY1 DATA ROUTING CH-1 CH-2 CH-3 Figure 4-9. Two PCM Sync Methods 4-18 MC68302 USER’S MANUAL MOTOROLA...
Page 139: Nonmultiplexed Serial Interface (Nmsi)
If the IDL or GCI mode is used, this register allows the user to support any or all of the ISDN channels independently. Any extra SCC channel can then be used for other purposes in MOTOROLA MC68302 USER’S MANUAL 4-19...
Page 140 This mode may be used to accomplish multiplex mode loopback testing without affecting the multiplexed layer 1 interface. It also prevents an SCC's indi- vidual loopback (configured in the SCM) from affecting the pins of its associated NMSI interface. 4-20 MC68302 USER’S MANUAL MOTOROLA...
Page 141 (RXD1, TXD1, RCLK1, TCLK1, CD1, CTS1, and RTS1). SCC2 functions can be routed to port A as NMSI functions or configured instead as PA6–PA0. Four of the SCC3 functions can be routed to port A or retained as PA11–PA8. The other MOTOROLA MC68302 USER’S MANUAL 4-21...
Page 142: Serial Interface Mask Register (Simask)
This configuration provides the user with options for controlling up to three independent full-duplex lines implementing bridges or gateway functions or multiplexing up to three SCCs onto the same physical layer interface to implement a 2B + D ISDN basic rate channel or 4-22 MC68302 USER’S MANUAL MOTOROLA...
Page 143 B pins as inputs in the port B data direction register. When a change in the state of the pin occurs, the interrupt handler may assert or negate the extra outputs to sup- port the hand-shaking protocol. (See 3.3 Parallel I/O Ports for related details.) MOTOROLA MC68302 USER’S MANUAL 4-23...
Page 144: Scc Features
4.5.2 SCC Configuration Register (SCON) Each SCC controller has a configuration register that controls its operation and selects its clock source and baud rate. Figure 4-12 shows one of the three SCC baud rate generators. 4-24 MC68302 USER’S MANUAL MOTOROLA...
Page 145 RCLK pin. This bit should be programmed to one if a multiplexed mode is chosen for the SCC. After system reset, SCC hardware causes the RCLK to default to an input and stay an input until a zero is written to RCS. MOTOROLA MC68302 USER’S MANUAL 4-25...
Page 146: Asynchronous Baud Rate Generator Examples
3 (programmed as 2 in the SCON) and a 16.67-MHz crystal gives a UART clock rate of 5.56 MHz and a baud rate of 347 kbaud. Assuming again a 16.67-MHz 4-26 MC68302 USER’S MANUAL MOTOROLA...
Page 147: Synchronous Baud Rate Generator Examples
00 = Normal operation (CTS, CD lines under automatic control) In this mode, the CTS and CD lines are monitored by the SCC controller. The SCC controller uses these lines to automatically enable/disable reception and transmission. MOTOROLA MC68302 USER’S MANUAL 4-27...
Page 148: Table 4-5. Transmit Data Delay (Tclk Periods)
The value on the RXD pin is ignored. For the NMSI2 and NMSI3 pins, the TXD pin may be programmed to either show the transmitted data or not show the data by programming port A par- 4-28 MC68302 USER’S MANUAL MOTOROLA...
Page 149: Figure 4-13. Output Delays From Rts Low, Synchronous Protocol
SDIAG1–SDIAG0 bits need be set. When using loopback mode, the clock source for the transmitter and the receiver (as set in the TCS and RCS bits in the SCON register), must be the same. Thus, MOTOROLA MC68302 USER’S MANUAL 4-29...
Page 150 The other two combinations are not allowed in this mode. NOTE If external loopback is desired (i.e., external to the MC68302), then the DIAG1–DIAG0 bits should be set for either normal or software operation, and an external connection should be made between the TXD and RXD pins.
Page 151: Scc Data Synchronization Register (Dsr)
Note that for the DDCMP, SYN1 must equal SYN2 must equal DSYN1 for proper operation. SYN2 SYN1 NOTE The DSR register has no relationship to the RS-232 signal “data set ready,” which is also abbreviated DSR. MOTOROLA MC68302 USER’S MANUAL 4-31...
Page 152: Buffer Descriptors Table
SCC1 BUFFER DESCRIPTORS FRAME STATUS TABLE DATA COUNT SCC2 BUFFER DESCRIPTORS DATA POINTER RX DATA BUFFER TABLE SCC3 BUFFER DESCRIPTORS DATA TABLE SCP DESCRIPTOR SMC1 DESCRIPTOR TX DATA SMC2 DESCRIPTOR RX DATA Figure 4-15. Memory Structure 4-32 MC68302 USER’S MANUAL MOTOROLA...
Page 153: Figure 4-16. Scc Buffer Descriptor Format
Thus, the CP does no look-ahead BD processing, nor does it skip over BDs that are not ready. When the CP sees the “wrap” bit set in a BD, it goes back to the beginning of the BD MOTOROLA MC68302 USER’S MANUAL 4-33...
Page 154: Scc Parameter Ram Memory Map
RAM areas. Part of each SCC parameter RAM (offset $80–$9A), which is iden- tical for each protocol chosen, is shown in Table 4-6. Offsets $9C–$BF comprise the proto- col-specific portion of the SCC parameter RAM and are discussed relative to the particular protocol chosen. 4-34 MC68302 USER’S MANUAL MOTOROLA...
Page 155: Data Buffer Function Code Register (Tfcr, Rfcr)
The value of the function code register for any channel may be equal to that of any other, but do not initialize FC2–FC0 with the value “111” which causes a conflict with the interrupt acknowl- edge cycle to occur. MOTOROLA MC68302 USER’S MANUAL 4-35...
Page 156: Maximum Receive Buffer Length Register (Mrblr)
Tx BD 1, TBD# = $48, etc. Upon reset, the CP main controller sets this register to $40. The user can change this register only after the STOP TRANSMIT command has been issued. In most applications, this parameter will never need to be modified by the user. 4-36 MC68302 USER’S MANUAL MOTOROLA...
Page 157: Other General Parameters
1. If SCC2 or SCC3 is used, write the parallel port A and B control registers (PACNT and PBCNT) to configure pins as parallel I/O lines or peripheral functions as needed (see 3.3 Parallel I/O Ports). 2. Write SIMODE to configure the serial channels physical interface for the three SCCs MOTOROLA MC68302 USER’S MANUAL 4-37...
Page 158: Interrupt Mechanism
SCC mask register). The SCC event register is a memory- mapped register that may be read at any time. A bit is cleared by writing a one (writing a zero does not affect a bit's value). 4-38 MC68302 USER’S MANUAL MOTOROLA...
Page 159: Scc Mask Register (Sccm)
NOTE After power-on reset, when the SCC is enabled for the first time, the SCCE register will show that a change of status occurred, re- MOTOROLA MC68302 USER’S MANUAL 4-39...
Page 160: Bus Error On Sdma Access
(see 3.2 Interrupt Controller). The interrupt service routine should read the bus error channel number from the parameter RAM at BASE + 67C as follows: 0—SCC1 Tx Channel 1—SCC1 Rx Channel or DRAM Refresh Cycle 2—SCC2 Tx Channel 3—SCC2 Rx Channel 4-40 MC68302 USER’S MANUAL MOTOROLA...
Page 161: Scc Transparent Mode
• If EXSYN in the BISYNC mode register is set, then the BISYNC controller transfers all characters that follow the external SYNC pulse to the receive buffers. NOTE The BISYNC controller can reverse the bit order in both modes. MOTOROLA MC68302 USER’S MANUAL 4-41...
Page 162: Disabling The Sccs
Communications Processor (CP) Totally Transparent (Promiscuous) Mode The MC68302 can both receive and transmit the entire serial bit stream transparently. See 4.5.16 Transparent Controller for details. 4.5.10 Disabling the SCCs If an SCC transmitter or receiver is not needed for a period of time or a mode change is re- quired, then it may be disabled and re-enabled later.
Page 163: Uart Controller
The character format of the UART protocol is shown in Figure 4-17. 7 OR 8 DATA BITS WITH THE LEAST SIGNIFICANT BIT FIRST OPTIONAL START ADDR. PAR. 9/16 TO 2 UART TXD STOP BITS UART TCLK Figure 4-17. UART Frame Format MOTOROLA MC68302 USER’S MANUAL 4-43...
Page 164 TXD line and receives data from the RXD line into memory. The seven dedicated serial interface pins are transmit data (TXD), receive data (RXD), receive clock (RCLK), transmit clock (TCLK), carrier detect (CD), clear to send (CTS), and request to send 4-44 MC68302 USER’S MANUAL MOTOROLA...
Page 165: Normal Asynchronous Mode
When a complete character has been clocked in, the contents of the shift register are transferred to the UART receive data register. If there is an error in this character, then the appropriate error bits will be set by the IMP. MOTOROLA MC68302 USER’S MANUAL 4-45...
Page 166: Asynchronous Ddcmp Mode
When configured to operate in UART mode, the IMP overlays the structure (see Table 4-6) onto the protocol-specific area of that SCC's parameter RAM. Refer to 2.8 MC68302 Mem- ory Map for the placement of the three SCC parameter RAM areas and to Table 4-5 for the other parameter RAM values.
Page 167 In the multidrop mode, the UART controller can provide automatic address recognition of two addresses. In this case, the lower order byte of UADDR1 and UADDR2 are pro- grammed by the user with the two desired addresses. See 4.5.11.6 UART Address Rec- ognition for more details. MOTOROLA MC68302 USER’S MANUAL 4-47...
Page 168: Uart Programming Model
Flow-control characters may also be transmitted at any time. In the message-oriented environment, the data stream is divided into buffers. However, the physical format of each character (stop bits, parity, etc.) is not altered. 4-48 MC68302 USER’S MANUAL MOTOROLA...
Page 169: Uart Command Set
If an enabled receiver has been disabled by clearing ENR in the SCC mode register, the ENTER HUNT MODE command must be given to the channel before setting ENR again. Reception will then begin with the next BD. MOTOROLA MC68302 USER’S MANUAL 4-49...
Page 170: Uart Address Recognition
SLAVE 3 SCON REGISTER WIRED-OR MODE SELECT TWO 8-BIT ADDRESSES UADDR1 ALLOWS MULTIPLE CAN BE AUTOMATICALLY TRANSMIT PINS TO BE RECOGNIZED IN EITHER UADDR2 DIRECTLY CONNECTED. CONFIGURATION. WOMS Figure 4-18. Two Configurations of UART Multidrop Operation 4-50 MC68302 USER’S MANUAL MOTOROLA...
Page 171: Uart Control Characters And Flow Control
OFFSET + CHARACTER8 Figure 4-19. UART Control Characters Table CHARACTER7–CHARACTER1—Control Character Value These fields define control characters that should be compared to the incoming character. For 7-bit characters, the eighth bit (bit 7) should be zero. MOTOROLA MC68302 USER’S MANUAL 4-51...
Page 172 The CP clears this bit after transmis- sion. I—Interrupt If set, the M68000 core will be interrupted when this character has been transmitted. (The TX bit will be set in the UART event register.) 4-52 MC68302 USER’S MANUAL MOTOROLA...
Page 173: Send Break
If the UART is still in the process of receiving a message that the user has already decided to discard, the message may be aborted by issuing the ENTER HUNT MODE command. The UART receiver will be re-enabled when the message is finished by detecting one idle MOTOROLA MC68302 USER’S MANUAL 4-53...
Page 174: Uart Error-Handling Procedure
5. Noise Error. Noise error is detected by the UART controller when the three samples taken on every bit are not identical. When this error occurs, the channel writes the re- ceived character to the buffer and proceeds normally but increments the noise error 4-54 MC68302 USER’S MANUAL MOTOROLA...
Page 175: Fractional Stop Bits
The UART receiver can always receive fractional stop bits. The next character's start bit may begin anytime after the 11th internal clock of the previous character's first stop bit (the UART uses a 16x clock). MOTOROLA MC68302 USER’S MANUAL 4-55...
Page 176: Uart Mode Register
01 = In the multidrop mode, an additional address/data bit is transmitted with each character. The multidrop asynchronous modes are compatible with the Motorola MC68681 DUART, the Motorola MC68HC11 SCI interface, and the Motorola DSP56000 SCI interface. UM0 is also used to select the wakeup mode before en- abling the receiver or issuing the ENTER HUNT MODE command.
Page 177: Uart Receive Buffer Descriptor (Rx Bd)
1. Reception of a user-defined control character (when reject (R) bit = 0) 2. Detection of an error during message processing 3. Detection of a full receive buffer 4. Reception of a programmable number of consecutive IDLE characters MOTOROLA MC68302 USER’S MANUAL 4-57...
Page 178: Figure 4-20. Uart Receive Buffer Descriptor
BD in the table, allowing the user to use fewer than eight BDs to conserve internal RAM. NOTE The user is required to set the wrap bit in one of the first eight BDs; otherwise, errant behavior may occur. 4-58 MC68302 USER’S MANUAL MOTOROLA...
Page 179: Figure 4-21. Uart Rx Bd Example
32-BIT BUFFER POINTER PROGRESS POINTER (MAX_IDL) (24-BITS USED) WITH THIS BUFFER 10 CHARS 5 CHARS LONG IDLE PERIOD CHARACTERS RECEIVED BY UART PRESENT FOURTH CHARACTER TIME HAS FRAMING ERROR! TIME Figure 4-21. UART Rx BD Example MOTOROLA MC68302 USER’S MANUAL 4-59...
Page 180 A framing error is detected by the UART controller when no stop bit is detected in the re- ceive data string. PR—Parity Error A character with a parity error was received and is located in the last byte of this buffer. OV—Overrun A receiver overrun occurred during message reception. 4-60 MC68302 USER’S MANUAL MOTOROLA...
Page 181: Uart Transmit Buffer Descriptor (Tx Bd)
1 = The data buffer, which has been prepared for transmission by the user, has not been transmitted or is currently transmitting. No fields of this BD may be written by the user once this bit is set. MOTOROLA MC68302 USER’S MANUAL 4-61...
Page 182 0 = No preamble sequence is sent. 1 = The UART sends one preamble sequence (9 to 13 ones) before sending the data. The following bits are written by the CP after it has finished transmitting the associated data buffer. 4-62 MC68302 USER’S MANUAL MOTOROLA...
Page 183: Uart Event Register
All unmasked bits must be cleared before the CP will clear the internal interrupt request. This register is cleared at reset. An example of the timing of various events in the UART event register is shown in Figure 4- MOTOROLA MC68302 USER’S MANUAL 4-63...
Page 184: Figure 4-23. Uart Interrupt Events Example
IDL—IDLE Sequence Status Changed A change in the status of the receive serial line was detected on the UART channel. The SCC status register may be read to determine the current status. 4-64 MC68302 USER’S MANUAL MOTOROLA...
Page 185: Uart Mask Register
(ENT, ENR) bits set. Receive buffers should be linked to the receive buffer table with the interrupt (I) bit set. For simplicity, assume that the line is not multidrop (no addresses are transmitted) and that each S record will fit into a single data buffer. MOTOROLA MC68302 USER’S MANUAL 4-65...
Page 186: Hdlc Controller
LAPD further di- vides its 16-bit address into different fields to specify various access points within one piece of equipment. It also defines a broadcast address. Some HDLC-type protocols also allow for extended addressing beyond 16-bits. 4-66 MC68302 USER’S MANUAL MOTOROLA...
Page 187 • Separate Interrupts for Frames and Buffers (Receive and Transmit) • Four Address Comparison Registers with Mask • Maintenance of Five 16-Bit Error Counters • Flag/Abort/Idle Generation/Detection • Zero Insertion/Deletion • NRZ/NRZI Data Encoding • 16-Bit or 32-Bit CRC-CCITT Generation/Checking MOTOROLA MC68302 USER’S MANUAL 4-67...
Page 188: Hdlc Channel Frame Transmission Processing
When the data buffer has been filled, the HDLC controller clears the empty bit in the BD and generates an interrupt if the interrupt bit in the BD is set. If the incoming frame ex- 4-68 MC68302 USER’S MANUAL MOTOROLA...
Page 189: Hdlc Memory Map
When configured to operate in HDLC mode, the IMP overlays the structure shown in Table 4-7 onto the protocol-specific area of that SCC parameter RAM. Refer to 2.8 MC68302 Memory Map for the placement of the three SCC parameter RAM areas and to Table 4-2 for the other parameter RAM values.
Page 190: Hdlc Command Set
BD (TBD#) in the channel's transmit BD table. If the transmitter is being re-enabled, the RESTART TRANSMIT command must be used and should be followed by the enabling of the transmitter in the SCC mode register. 4-70 MC68302 USER’S MANUAL MOTOROLA...
Page 191: Hdlc Address Recognition
HDLC frame is discarded, and the LG (Rx frame too long) bit is set in the last BD belonging to that frame. The HDLC controller waits to the end of the frame and reports the frame status MOTOROLA MC68302 USER’S MANUAL 4-71...
Page 192: Hdlc Error-Handling Procedure
BD of length two will be opened to report the overrun, and the RXB interrupt will be generated (if enabled). 2. Carrier Detect Lost During Frame Reception. When this error occurs and the channel 4-72 MC68302 USER’S MANUAL MOTOROLA...
Page 193: Hdlc Mode Register
RETRC—Frame Retransmission Counter (due to collision) 4.5.12.9 HDLC Mode Register Each SCC mode register is a 16-bit, memory-mapped, read-write register that controls the SCC operation. The term HDLC mode register refers to the protocol-specific bits (15–6) of MOTOROLA MC68302 USER’S MANUAL 4-73...
Page 194 This bit may be dynamically modified. If toggled from a one to a zero between frames, a maximum of two additional flags will be transmitted before the idle condition will begin. Toggling FLG will never result in partial flags being transmitted. 4-74 MC68302 USER’S MANUAL MOTOROLA...
Page 195: Hdlc Receive Buffer Descriptor (Rx Bd)
HDLC controller is currently filling the buffer with received data. X—External Buffer 0 = The buffer associated with this BD is in internal dual-port RAM. 1 = The buffer associated with this BD is in external memory. MOTOROLA MC68302 USER’S MANUAL 4-75...
Page 196: Figure 4-27. Hdlc Receive Bd Example
PRESENT UNEXPECTED ABORT TIME OCCURS BEFORE TIME CLOSING FLAG! LEGEND: F = FLAG I = INFORMATION BYTE A = ADDRESS BYTE CR = CRC BYTE C = CONTROL BYTE Figure 4-27. HDLC Receive BD Example 4-76 MC68302 USER’S MANUAL MOTOROLA...
Page 197 BD. NO—Rx Nonoctet Aligned Frame A frame that contained a number of bits not exactly divisible by eight was received. AB—Rx Abort Sequence A minimum of seven consecutive ones was received during frame reception. MOTOROLA MC68302 USER’S MANUAL 4-77...
Page 198: Hdlc Transmit Buffer Descriptor (Tx Bd)
— — — — — — — — OFFSET + 2 OFFSET + 4 DATA LENGTHTX BUFFER POINTER (24-bits used, upper 8 bits must be 0) OFFSET + 6 Figure 4-28. HDLC Transmit Buffer Descriptor 4-78 MC68302 USER’S MANUAL MOTOROLA...
Page 199 1 = Transmit the CRC sequence after the last data byte. Bits 9–2—Reserved for future use. The following status bits are written by the HDLC controller after it has finished transmitting the associated data buffer. MOTOROLA MC68302 USER’S MANUAL 4-79...
Page 200: Hdlc Event Register
All unmasked bits must be cleared before the CP will clear the internal interrupt request. This register is cleared at reset. An example of the timing of various events in the HDLC event register is shown in Figure 4- 4-80 MC68302 USER’S MANUAL MOTOROLA...
Page 201: Figure 4-29. Hdlc Interrupt Events Example
CD—Carrier Detect Status Changed A change in the status of the CD line was detected on the HDLC channel. The SCC status register may be read to determine the current status. MOTOROLA MC68302 USER’S MANUAL 4-81...
Page 202: Hdlc Mask Register
Each class of frame starts with a standard two octet synchroni- zation pattern and ends with a block check code (BCC). The end of text character (ETX) is used to separate the text and BCC fields. 4-82 MC68302 USER’S MANUAL MOTOROLA...
Page 203: Figure 4-30. Typical Bisync Frames
The BISYNC controller consists of separate transmit and receive sections whose operations are asynchronous with the M68000 core and may be either synchronous or asynchronous with respect to the other SCCs. Each clock can be supplied from either the internal baud MOTOROLA MC68302 USER’S MANUAL 4-83...
Page 204: Bisync Channel Frame Transmission Processing
SYN1–SYN2 pair followed by either SYNCs or idles according to the SYNF bit in the BISYNC mode register. This case is an underrun error and is described further in 4.5.13.8 BISYNC Error-Handling Procedure. 4-84 MC68302 USER’S MANUAL MOTOROLA...
Page 205: Bisync Channel Frame Reception Processing
See 4.5.16 Transparent Controller. 4.5.13.3 Bisync Memory Map When configured to operate in BISYNC mode, the IMP overlays the structure listed in Table 4-8 onto the protocol-specific area of that SCC parameter RAM. Refer to 2.8 MC68302 MOTOROLA MC68302 USER’S MANUAL...
Page 206: Bisync Command Set
TBD# is not advanced. SYNC characters consisting of SYNC-SYNC or DLE-SYNC pairs (according to the transmitter mode) will be continually transmitted until transmission is re- enabled by issuing the RESTART TRANSMIT command. The STOP TRANSMIT com- 4-86 MC68302 USER’S MANUAL MOTOROLA...
Page 207: Bisync Control Character Recognition
DMA-oriented environment. Their main use is for receive buff- ers longer than one byte. In single-byte buffers, each byte can easily be inspected, and con- trol character recognition should be disabled. MOTOROLA MC68302 USER’S MANUAL 4-87...
Page 208: Figure 4-31. Bisync Control Characters Table
E—End of Table 0 = This entry is valid. The lower eight bits will be checked against the incoming char- acter. 1 = The entry is not valid. No valid entries exist beyond this entry. 4-88 MC68302 USER’S MANUAL MOTOROLA...
Page 209: Bsync-Bisync Sync Register
When the BISYNC receiver is in transparent mode and a DLE character is received, the re- ceiver discards this character and excludes it from the BCS if the valid (V) bit is set. If the second (next) character is a SYNC character, the BISYNC controller discards it and ex- MOTOROLA MC68302 USER’S MANUAL 4-89...
Page 210: Bisync Error-Handling Procedure
RX interrupt (if enabled). This error is the highest priority; the rest of the message is lost and no other errors are checked in the message. The receiver then enters hunt mode immediately. 3. Parity Error. When this error occurs, the channel writes the received character to the 4-90 MC68302 USER’S MANUAL MOTOROLA...
Page 211: Bisync Mode Register
L1SY1 pin. In PCM mode, the L1SY1–L1SY0 pins are used. In NMSI mode, the CD pins (and the CD timing) are used to synchronize the data. CD should be asserted on the second data bit of the frame when used as a sync. MOTOROLA MC68302 USER’S MANUAL 4-91...
Page 212 The BISYNC receiver internally stores two BCS calculations with a byte delay (eight serial clocks) between them. This enables the user to examine a received data byte and then decide whether or not it should be part of the BCS calculation. This is useful when control 4-92 MC68302 USER’S MANUAL MOTOROLA...
Page 213: Bisync Receive Buffer Descriptor (Rx Bd)
BD. 1 = The data buffer associated with this BD is empty. This bit signifies that the BD and its associated buffer are available to the CP. After it sets this bit, the M68000 core MOTOROLA MC68302 USER’S MANUAL 4-93...
Page 214 While in transparent mode, a DLE character was received, and the next character was not DLE, SYNC, or a valid entry in the control characters table. PR—Parity Error A character with a parity error was received and is the last byte of this buffer. 4-94 MC68302 USER’S MANUAL MOTOROLA...
Page 215: Bisync Transmit Buffer Descriptor (Tx Bd)
Figure 4-33. BISYNC Transmit Buffer Descriptor The first word of the Tx BD contains status and control bits. These bits are prepared by the user before transmission and are set by the CP after the buffer has been transmitted. MOTOROLA MC68302 USER’S MANUAL 4-95...
Page 216 1 = Buffer consists of characters to be included in the BCS accumulation. BR—BCS Reset 0 = The BCS accumulation is not reset. 1 = The transmitter BCS accumulation is reset (used for STX or SOH) before sending the data buffer. 4-96 MC68302 USER’S MANUAL MOTOROLA...
Page 217: Bisync Event Register
4.5.13.12 BISYNC Event Register The SCC event register (SCCE) is referred to as the BISYNC event register when the SCC is programmed as a BISYNC controller. It is an 8-bit register used to report events recog- MOTOROLA MC68302 USER’S MANUAL 4-97...
Page 218: Bisync Mask Register
BISYNC event register. If a bit in the BISYNC mask register is a one, the cor- responding interrupt in the event register will be enabled. If the bit is zero, the corresponding interrupt in the event register will be masked. This register is cleared upon reset. 4-98 MC68302 USER’S MANUAL MOTOROLA...
Page 219: Programming The Bisync Controllers
Control Characters Next Entry After the end of text (ETX), a BCS is expected; then the buffer should be closed. Hunt mode should be entered when line turnaround occurs. ENQ characters are used to abort transmis- MOTOROLA MC68302 USER’S MANUAL 4-99...
Page 220: Ddcmp Controller
Asynchronous DDCMP frames are composed of asynchronous UART characters, which together form the frame. The receiver and transmit- ter clocks are not linked; the receiver resynchronizes itself every byte using the start and stop bits of each UART character. 4-100 MC68302 USER’S MANUAL MOTOROLA...
Page 221: Ddcmp Channel Frame Transmission Processing
(BD) in the channel's transmit BD table. When there is a message to transmit, the DDCMP controller fetches the data from memory and starts transmitting the message (after first transmitting the SYN1–SYN2 pair when the link is synchronous). MOTOROLA MC68302 USER’S MANUAL 4-101...
Page 222: Ddcmp Channel Frame Reception Processing
SYN1–SYN2 fields of the data synchronization register (see 4.5.4 SCC Data Synchroniza- tion Register (DSR)). If the two are not equal, the next bit is shifted in, and the comparison is repeated. When the registers match, hunt mode is terminated, and character assembly 4-102 MC68302 USER’S MANUAL MOTOROLA...
Page 223: Ddcmp Memory Map
When configured to operate in DDCMP mode, the IMP overlays the structure illustrated in Table 4-9 onto the protocol-specific area of that SCC's parameter RAM. Refer to 2.8 MC68302 Memory Map for the placement of the three SCC parameter RAM areas and to Table 4-5 for the other parameter RAM values.
Page 224: Ddcmp Programming Model
BD in the table approximately every eight transmit clocks. The channel STOP TRANSMIT command disables the transmission of messages on the transmit channel. If this command is received by the DDCMP controller during message 4-104 MC68302 USER’S MANUAL MOTOROLA...
Page 225: Ddcmp Control Character Recognition
The 8-bit DSYN1 register should be written with the same value that was written in the SYN1 byte of the data synchronization register (DSR). DSYN1 is a memory-mapped read-write register. NOTE For correct operation of DDCMP, DSYN1, SYN1, and SYN2 must be the same value. MOTOROLA MC68302 USER’S MANUAL 4-105...
Page 226: Ddcmp Address Recognition
(UN) bit in the BD, and generates the trans- mit error (TXE) interrupt (if enabled). The channel will resume transmission after the reception of the RESTART TRANSMIT command. The FIFO size is three bytes. 4-106 MC68302 USER’S MANUAL MOTOROLA...
Page 227 (FR) bit in the BD, and generates the RBK interrupt (if enabled). When this error occurs, parity is not checked for this character. MOTOROLA MC68302 USER’S MANUAL 4-107...
Page 228: Ddcmp Mode Register
If NOS3–NOS0 = 0000, then 1 SYNC pair will be transmitted; if NOS3–NOS0 = 1111, then 16 SYNC pairs will be transmitted. NOTE With appropriate programming of the transmit BD (TC = 1 and L = 0), it is possible to transmit back-to-back messages. 4-108 MC68302 USER’S MANUAL MOTOROLA...
Page 229: Ddcmp Receive Buffer Descriptor (Rx Bd)
The first word of the Rx BD contains control and status bits. Bits 15–12 are written by the user before the buffer is linked to the Rx BD table, and bits 5–0 and 11–8 are set by the IMP MOTOROLA MC68302 USER’S MANUAL 4-109...
Page 230 1 = The buffer contains a message header. NOTE To correctly identify buffers containing headers, the buffer size should be eight or more bytes in length so that the header will fit in a single buffer. 4-110 MC68302 USER’S MANUAL MOTOROLA...
Page 231 It is written by the CP once as the BD is closed. NOTE The actual buffer size should be greater than or equal to eight (to ensure the header is received in one buffer). MOTOROLA MC68302 USER’S MANUAL 4-111...
Page 232: Ddcmp Transmit Buffer Descriptor (Tx Bd)
1 = This is the last BD in the Tx BD table. After this buffer has been used, the DDCMP controller will transmit data from the first BD in the table. NOTE The user is required to set the wrap bit in one of the first eight BDs; otherwise, errant behavior may occur. 4-112 MC68302 USER’S MANUAL MOTOROLA...
Page 233 The DDCMP controller encountered a transmitter underrun condition while transmitting the associated data buffer. NOTE This error can occur only on synchronous links. CT—CTS Lost CTS in NMSI mode or grant in IDL/GCI mode was lost during message transmission. MOTOROLA MC68302 USER’S MANUAL 4-113...
Page 234: Ddcmp Event Register
A complete block has been received on the DDCMP channel. A block is defined as recep- tion of a complete header, a complete message, or a receiver error condition. BSY—Busy Condition A data byte was received and discarded due to lack of buffers. The receiver will enter hunt mode automatically. 4-114 MC68302 USER’S MANUAL MOTOROLA...
Page 235: Ddcmp Mask Register
Another rate adaption protocol, called V.120, is an alternative protocol to V.110. V.120 is an extension of the LAPD protocol and may be implemented on the MC68302 using an SCC configured in HDLC mode.
Page 236: Bit Rate Adaption Of Synchronous Data Signaling Rates Up To 19.2 Kbps
V.110 operation (see 4.5.9 SCC Transparent Mode). The M68000 core will need to format the framing pattern in the 48-kbps conversion case. For the 56-kbps rate conversion, however, the B channel mask (SIMASK) in the serial channel physical interface can be used. 4-116 MC68302 USER’S MANUAL MOTOROLA...
Page 237: Adaption For Asynchronous Rates Up To 19.2 Kbps
Another SCC controller may be used to receive data from the R interface. The M68000 core should then format the data according to the V.110 protocol to create the V.110 80-bit frame data buffer. The V.110 controller will then transmit it onto the B channel. MOTOROLA MC68302 USER’S MANUAL 4-117...
Page 238: Programming Model
• Receiving of 10 bytes (80-bit frame) • Detecting of an error • Issuing the ENTER HUNT MODE command 4-118 MC68302 USER’S MANUAL MOTOROLA...
Page 239: Figure 4-40. V.110 Receive Buffer Descriptor
A frame with a synchronization error was received. A synchronization error is detected by the V.110 controller when the MSB of a byte (except the all-zeros byte) is not one. OV—Overrun A receiver overrun occurred during message reception. MOTOROLA MC68302 USER’S MANUAL 4-119...
Page 240: Transmit Buffer Descriptor (Tx Bd)
No fields of this BD may be written by the user once this bit is set. X—External Buffer 0 = The buffer associated with this BD is in internal dual-port RAM. 1 = The buffer associated with this BD is in external memory. 4-120 MC68302 USER’S MANUAL MOTOROLA...
Page 241: Event Register
The SCC event register (SCCE) is referred to as the V.110 event register when the SCC is configured as a V.110 controller. It is an 8-bit register used to report events recognized by the V.110 channel and to generate interrupts. On recognition of an event, the V.110 control- MOTOROLA MC68302 USER’S MANUAL 4-121...
Page 242: Mask Register
Often this conversion is performed to allow communication between chips on the same board. The SCCs on the MC68302 can do this very efficiently with very little M68000 core intervention. Third, some applications require the switching of data without interfering with 4-122 MC68302 USER’S MANUAL...
Page 243: Transparent Channel Buffer Transmission Processing
M68000 core and may be either synchronous or asynchro- nous with respect to the other SCCs. Transparent mode on the MC68302 is a synchronous protocol; thus, a clock edge must be provided with each bit of data received or transmitted.
Page 244: Transparent Channel Buffer Reception Processing
Once synchronization is achieved for the receiver, the reception process continues unabat- ed until a busy condition occurs, a CD lost condition occurs, or a receive overrun occurs. The busy condition error should be followed by an ENTER HUNT MODE command to the 4-124 MC68302 USER’S MANUAL MOTOROLA...
Page 245: Transparent Memory Map
When configured to operate in transparent mode, the IMP overlays the structure illustrated in Table 4-11 onto the protocol specific area of that SCC parameter RAM. Refer to 2.8 MC68302 Memory Map for the placement of the three SCC parameter RAM areas and Ta- ble 4-5 for the other parameter RAM values.
Page 246: Transparent Commands
SCC, and the transmit FIFO has been preloaded by the SDMA channel (signaled by the RTS pin in NMSI and PCM modes), one additional process must occur before data can be transmitted and received. This process is called 4-126 MC68302 USER’S MANUAL MOTOROLA...
Page 247 SYN bit in the SCM, and, in some cases, the data synchronization register (DSR). The re- sulting timing is dependent on the physical interface chosen. NOTE See D.8 Using the MC68302 Transparent Mode for timing dia- grams and additional details concerning mode. Five ways exist to achieve transparent synchronization.
Page 248: Transparent Error-Handling Procedure
FIFO. If a FIFO overrun occurs, the transparent controller writes the received data word to the internal FIFO over the previously received word. The previous word is lost. Next, the channel closes 4-128 MC68302 USER’S MANUAL MOTOROLA...
Page 249: Transparent Mode Register
This bit must be set for the SCC to operate in a totally transparent (promiscuous) mode. REVD—Reverse Data When this bit is set, the receiver and transmitter will reverse the character bit order, trans- mitting the most significant bit first. MOTOROLA MC68302 USER’S MANUAL 4-129...
Page 250: Transparent Receive Buffer Descriptor (Rxbd)
BD in the table. Setting this bit allows the use of fewer than eight BDs to conserve internal RAM. NOTE The user is required to set the wrap bit in one of the first eight BDs; otherwise, errant behavior may occur. 4-130 MC68302 USER’S MANUAL MOTOROLA...
Page 251: Transparent Transmit Buffer Descriptor (Tx Bd)
Figure 4-43. Transparent Transmit Buffer Descriptor The first word of the Tx BD contains status and control bits. These bits are prepared by the user before transmission and are set by the CP after the buffer has been transmitted. MOTOROLA MC68302 USER’S MANUAL 4-131...
Page 252 UN—Underrun The transparent controller encountered a transmitter underrun condition while transmit- ting the associated data buffer. CT—CTS Lost CTS in NMSI mode or L1GR in IDL/GCI mode was lost during frame transmission. 4-132 MC68302 USER’S MANUAL MOTOROLA...
Page 253: Transparent Event Register
A word has been received and written to the receive buffer. BSY—Busy Condition A word was received and discarded due to lack of buffers. The receiver will resume re- ception after an ENTER HUNT MODE command. MOTOROLA MC68302 USER’S MANUAL 4-133...
Page 254: Transparent Mask Register
Since the MC68302 is an SCP master for this serial channel, it generates both the enable and the clock signals.
Page 255: Figure 4-44. Scp Timing
Note that the least significant bit of the SCP is labeled as data bit 0 on the serial line; where- as, other devices, such as the MC145554 CODEC, may label the most significant bit as data bit 0. The MC68302 SCP bit 7 (most significant bit) is shifted out first. The SCP key features are as follows: •...
Page 256: Scp Programming Model
When the DIAG1–DIAG0 bits of SCC3 are programmed to nor- mal operation control of the CTS and CD lines and the ENT or ENR bits of SCC3 are set, the user may not modify the EN bit. 4-136 MC68302 USER’S MANUAL MOTOROLA...
Page 257: Scp Transmit/Receive Buffer Descriptor
Upon recognizing the STR bit, the SCP also begins receiving eight bits of data. It writes the data into the transmit/receive BD, clears the done bit, and issues a maskable interrupt to the IMP interrupt controller. When working in a polled environment, the done bit should be set MOTOROLA MC68302 USER’S MANUAL 4-137...
Page 258: Serial Management Controllers (Smcs)
The SMCs are two synchronous, full-duplex serial management control (SMC) ports. The SMC ports may be configured to operate in either Motorola interchip digital link (IDL) or gen- eral circuit interface (GCI) modes. GCI is also known as ISDN oriented modular 2 (IOM-2).
Page 259: Smc Programming Model
The operating mode of both SMC ports is defined by SMC mode, which consists of the lower eight bits of SPMODE. As previously mentioned, the upper eight bits program the SCP. — SMD3 SMD2 SMD1 SMD0 LOOP MOTOROLA MC68302 USER’S MANUAL 4-139...
Page 260: Smc Commands
RAM of the IMP (see Figure 3-4). The SMC buffer descriptors allow the user to define one data byte at a time for each transmit channel and receive one data byte at a time for each receive channel. 4-140 MC68302 USER’S MANUAL MOTOROLA...
Page 261: Smc1 Receive Buffer Descriptor
This bit is valid only in GCI mode when the monitor channel is in transparent mode. EB—Received E Bit This bit is valid only in GCI mode when the monitor channel is in transparent mode. Data—Data Field The data field contains the byte of data received by SMC1. MOTOROLA MC68302 USER’S MANUAL 4-141...
Page 262: Smc1 Transmit Buffer Descriptor
The data field contains the data to be transmitted by SMC1. 4.7.4.3 SMC2 Receive Buffer Descriptor In the IDL mode, this BD is identical to the SMC1 receive BD. In the GCI mode, SMC2 is used to control the C/I channel. RESERVED 4-142 MC68302 USER’S MANUAL MOTOROLA...
Page 263: Smc2 Transmit Buffer Descriptor
Each of the two interrupt requests from each SMC is enabled when its respective SMC channel is enabled in the SPMODE register. Interrupt requests from SMC1 and SMC2 can be masked in the interrupt mask register. See 3.2 Interrupt Controller for more details. MOTOROLA MC68302 USER’S MANUAL 4-143...
Page 264 Communications Processor (CP) 4-144 MC68302 USER’S MANUAL MOTOROLA...
Page 265: Signal Description
SECTION 5 SIGNAL DESCRIPTION This section defines the MC68302 pinout. The input and output signals of the MC68302 are organized into functional groups and are described in the following sections. The MC68302 is offered in a 132-pin (13 x 13) pin grid array (PGA), a 132-lead plastic quad flat package (PQFP), and a 144-lead thin quad flat package (TQFP).
Page 266: Power Pins
V -0.3 and .6 volts and a high voltage of between 4.0 and V volts. This EXTAL signal must be present within 20 mS after V reaches its minimum specified level of 4.5 volts. MC68302 USER’S MANUAL MOTOROLA...
Page 267: Signal Description
CHIP SELECT TIN1 / PB3 CS0 / IOUT2 TOUT1 / PB4 CS3–CS1 TIN2 / PB5 TESTING TOUT2 / PB6 WDOG / PB7 PBIO (INTERRUPT) N.C.(2) GND(13) PB10 V DD (8) PB11 Figure 5-1. Functional Signal Groups MOTOROLA MC68302 USER’S MANUAL...
Page 268: Clocks
V reaches its minimum specified level of 4.5 volts. The frequency range of the original MC68302 was 8 MHz to 16.67 MHz. Thus, in this man- ual, many references to the frequency “16.67 MHz” are made when the maximum oper- ating frequency of the MC68302 is discussed.
Page 269: System Control
MC68302. RESET and HALT should remain asserted for at least 100 ms at power-on re- set, and at least 10 clocks otherwise. The on-chip system RAM is not initialized during re- set except for several locations initialized by the CP.
Page 270 This signal is asserted with the RESET signal to cause a total MC68302 system reset. If BERR is as- serted with the HALT signal, a retry cycle is performed.
Page 271: Address Bus Pins (A23-A1)
This 16-bit, bidirectional, three-state bus is the general-purpose data path. It can transmit and accept data in either word or byte lengths. For all 16-bit IMP accesses, byte 0, the high- order byte of a word, is available on D15–D8, conforming to the standard M68000 format. MOTOROLA MC68302 USER’S MANUAL...
Page 272: Bus Control Pins
IMP bus master or for an ex- ternal bus master access to an external address within the chip-select ranges. It will also be generated internally during any access to the on-chip dual-port RAM or internal regis- MC68302 USER’S MANUAL MOTOROLA...
Page 273: Figure 5-7. External Address/Data Buffer
Figure 5-7. The IAC signal saves the propagation delay and logic required to OR all the various system chip-select lines together to determine when to enable the external buffers. OTHER MASTER/SLAVE OTHER MASTER/SLAVE BUFFERS OTHER SLAVE Figure 5-7. External Address/Data Buffer MOTOROLA MC68302 USER’S MANUAL...
Page 274: Bus Arbitration Pins
If the SDMA steals a cycle from the IDMA, the BGACK pin will remain asserted continuously. NOTE BGACK should always be used in the external bus arbitration process. See 3.8.5.2 External Bus Arbitration for details. 5-10 MC68302 USER’S MANUAL MOTOROLA...
Page 275: Interrupt Control Pins
FC2–FC0 and A19–A16 to ensure that the in- terrupt is properly recognized. As IRQ1, IRQ6, and IRQ7 (dedicated mode), these inputs indicate to the MC68302 that an external device is requesting an interrupt. Level 7 is the highest level and cannot be masked.
Page 276: Mc68302 Bus Interface Signal Summary
IMP interrupt controller to an external CPU when the M68000 core is disabled. 5.10 MC68302 BUS INTERFACE SIGNAL SUMMARY Table 5-2 and Table 5-3 summarize all bus signals discussed in the previous paragraphs.
Page 277: Physical Layer Serial Interface Pins
SCC1/SCC2/SCC3 NMSI2 (8) SCC2 Controller PIO—Port A Parallel I/O NMSI3 (5) SCC3 Controller PIO—Port A Parallel I/O NMSI3 (3) SCC3 Controller SCP Controller NOTE: Each one of the parallel I/O pins can be conﬁgured individually. MOTOROLA MC68302 USER’S MANUAL 5-13...
Page 278: Typical Serial Interface Pin Configurations
The NMSI1 or ISDN interface pins are shown in Figure 5-10. RXD1 / L1RXD TXD1 / L1TXD RCLK1 / L1CLK TCLK1 / L1SY0 / SDS1 MC68302 CD1 / L1SY1 CTS1 / L1GR RTS1 / L1RQ / GCIDCL BRG1 Figure 5-10. NMSI1 or ISDN Interface Pins 5-14 MC68302 USER’S MANUAL MOTOROLA...
Page 279: Table 5-7. Mode Pin Functions
SCC1 is working with an external clock and is an output when SCC1 is working with its baud rate generator. The TCLK1 output can be three-stated by setting bit 13 in the CKCR register (see 3.9 Clock Control Register). MOTOROLA MC68302 USER’S MANUAL 5-15...
Page 280: Table 5-8. Pcm Mode Signals
If this pin is not used as a grant signal in GCI mode, it should be connected to V If the CTS1 pin has changed for more than one transmit clock cycle, the IMP asserts the appropriate bit in the SCC1 event register and optionally aborts the transmission of that frame. 5-16 MC68302 USER’S MANUAL MOTOROLA...
Page 281: Nmsi2 Port Or Port A Pins
SCC2 baud rate generator, unless SDS2 is enabled to be asserted during the B1 or B2 channels of ISDN (bits SDC2–SDC1 of SIMODE). SDS2/BRG2 may be temporarily disabled by configuring it as a general-purpose output pin. The input buffers have Schmitt MOTOROLA MC68302 USER’S MANUAL 5-17...
Page 282: Nmsi3 Port Or Port A Pins Or Scp Pins
SCP port. Otherwise, they are connected to the SCC3 port. Each of the port A I/O pins can be configured individually to be general-purpose I/O pins or a dedicated function in NMSI3. When they are used as the NMSI3 pins, they function exactly 5-18 MC68302 USER’S MANUAL MOTOROLA...
Page 283: Idma Or Port A Pins
IDMA, it can be configured as a general-purpose I/O pin. If the IDMA is used for memory-to-memory transfers only, then all three pins can be used as general-purpose I/O pins. The input buffer of DACK has a Schmitt trigger. MOTOROLA MC68302 USER’S MANUAL 5-19...
Page 284: Iack Or Pio Port B Pins
As IACK1, IACK6, and IACK7, these active low output signals indicate to the external device that the MC68302 is executing an interrupt acknowledge cycle. The external device must then place its vector number on the lower byte of the data bus or use AVEC for autovectoring (unless internal vector generation is used).
Page 285: Figure 5-15. Timer Pins
16 clock (CLKO) cycles and may be externally connected to the RE- SET and HALT pins to reset the MC68302. WDOG is never asserted by the on-chip hardware watchdog (see the BERR signal description). The WDOG pin function is enabled after a total system reset.
Page 286: Parallel I/O Pins With Interrupt Capability
RAM or registers (including the BAR, SCR, or CKCR registers). When the M68000 core is disabled, this pin operates as IOUT2. IOUT2—IOUT0 provide the interrupt request output signals from the IMP interrupt controller to an external CPU when the M68000 core is disabled. 5-22 MC68302 USER’S MANUAL MOTOROLA...
Page 287: No-Connect Pins
Unused I/O pins may be configured as outputs after reset and left unconnect- If the MC68302 is to be held in reset for extended periods of time in an application (other than what occurs in normal power-on reset or board test sequences) due to a special appli- cation requirement (such as V dropping below required specifications, etc.), then three-...
Page 288 Signal Description 5-24 MC68302 USER’S MANUAL MOTOROLA...
Page 289: Electrical Characteristics
For T = 70 C and P + 0 W, 16.67 MHz, 5.5 V, and CQFP package, the worst case value of T = 70 C + (5.5 V 30 mA 40 C/W) = 98.65C MOTOROLA MC68302 USER’S MANUAL...
Page 290: Power Considerations
(3) by measuring P D (at equilibrium) for a known T A . Using this value of K the values of P and T can be obtained by solving equations (1) and (2) iteratively for any value of T MC68302 USER’S MANUAL MOTOROLA...
Page 291: Power Dissipation
3.The M68000 core will not operate at 4 MHz. This is only for low power mode. MOTOROLA MC68302 USER’S MANUAL...
Page 292 For an I between 400 A and I mA, the minimum V is calculated as: V - (1 +.05 V/mA(I -.400 mA)). NOTE: All AC specs are assume an output load of 130pf (except for CLKO). MC68302 USER’S MANUAL MOTOROLA...
Page 293: Dc Electrical Characteristics-Nmsi1 In Idl Mode
2. CLKO skew from the rising and falling edges of EXTAL will not differ from each other by more than 1 ns, if the EXTAL rise time equals the EXTAL fall time. 3. You may not stop the clock input at any time. = 4V EXTAL = 0.6V CLKO Figure 6-1. Clock Timing Diagram MOTOROLA MC68302 USER’S MANUAL...
Page 294: Ac Electrical Specifications-Imp Bus Master Cycles
Clock High to BG Asserted — — — CHGL Clock High to BG Negated — — — CHGH BR Asserted to BG Asserted (see Note 11) clks BRLGL BR Negated to BG Negated (see Note 7) clks BRHGH MC68302 USER’S MANUAL MOTOROLA...
Page 295 X, where X is the difference between the nominal pulse width and the minimum pulse width of the EXTAL input clock for that duty cycle. 3. If #47 is satisﬁed for both DTACK and BERR, #48 may be ignored. In the absence of DTACK, BERR is a MOTOROLA MC68302 USER’S MANUAL...
Page 296 (#47). 4. For power-up, the MC68302 must be held in the reset state for 100 ms to allow stabilization of on-chip circuit. After the system is powered up #56 refers to the minimum pulse width required to reset the processor.
Page 297: Figure 6-2. Read Cycle Timing Diagram
The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0.8 volts and 2.0 volts. Figure 6-2. Read Cycle Timing Diagram MOTOROLA MC68302 USER’S MANUAL...
Page 298: Figure 6-3. Write Cycle Timing Diagram
2. Because of loading variations, R/W may be valid after AS even though both are initiated by the rising edge of S2 (specification #20A) 3. Each wait state is a full clock cycle inserted between S4 and S5. Figure 6-3. Write Cycle Timing Diagram 6-10 MC68302 USER’S MANUAL MOTOROLA...
Page 299: Figure 6-4. Read-Modify-Write Cycle Timing Diagram
4. Wait states may be inserted between S4 and S5 during the write cycle and between S16 and S17 during the read cycle. 5. Read-modify-write cycle is generated only by the TAS instruction. Figure 6-4. Read-Modify-Write Cycle Timing Diagram MOTOROLA MC68302 USER’S MANUAL 6-11...
Page 300: Figure 6-5. Bus Arbitration Timing Diagram
Electrical Characteristics Figure 6-5. Bus Arbitration Timing Diagram 6-12 MC68302 USER’S MANUAL MOTOROLA...
Page 301: Ac Electrical Specifications-Dma
4. Speciﬁcations are for DISABLE CPU mode only. 5. DREQ, DACK, and DONE do not apply to the SDMA channels. 6. DMA and SDMA read and write cycle timing is the same as that for the M68000 core. MOTOROLA MC68302 USER’S MANUAL 6-13...
Page 302: Figure 6-6. Dma Timing Diagram (Idma)
Electrical Characteristics Figure 6-6. DMA Timing Diagram (IDMA) 6-14 MC68302 USER’S MANUAL MOTOROLA...
Page 303: Figure 6-7. Dma Timing Diagram (Sdma)
Electrical Characteristics Figure 6-7. DMA Timing Diagram (SDMA) MOTOROLA MC68302 USER’S MANUAL 6-15...
Page 304: Ac Electrical Specifications-External Master Internal Asynchronous Read/Write Cycles
DS High to Data-Out Hold Time (see Note) — — — DSHDH 109A Data Out Valid to DTACK Low — — — DOVDKL NOTE: If AS is negated before DS, the data bus could be three-stated (spec 126) before DS is negated. 6-16 MC68302 USER’S MANUAL MOTOROLA...
Page 305: Figure 6-8. External Master Internal Asynchronous Read Cycle Timing Diagram
Electrical Characteristics Figure 6-8. External Master Internal Asynchronous Read Cycle Timing Diagram MOTOROLA MC68302 USER’S MANUAL 6-17...
Page 306: Figure 6-9. External Master Internal Asynchronous Write Cycle Timing Diagram
Electrical Characteristics Figure 6-9. External Master Internal Asynchronous Write Cycle Timing Diagram 6-18 MC68302 USER’S MANUAL MOTOROLA...
Page 307: Ac Electrical Specifications-External Master Internal Synchronous Read/Write Cycles
2. It is required that this signal not be asserted prior to the previous rising CLKO edge (i.e., in the previous clock cycle). It must be recognized by the IMP no sooner than the rising CLKO edge shown in the diagram. MOTOROLA MC68302 USER’S MANUAL 6-19...
Page 308: Figure 6-10. External Master Internal Synchronous Read Cycle Timing Diagram
Electrical Characteristics CLKO (OUTPUT) A23-A1 (INPUT) (INPUT) (OUTPUT) (INPUT) (INPUT) D15–D0 (OUTPUT) DTACK (OUTPUT) Figure 6-10. External Master Internal Synchronous Read Cycle Timing Diagram 6-20 MC68302 USER’S MANUAL MOTOROLA...
Page 309 Electrical Characteristics CLKO (OUTPUT) A23–A1 (INPUT) (INPUT) (OUTPUT) (INPUT) (INPUT) D15–D0 (OUTPUT) DTACK (OUTPUT) Figure 6-11. External Master Internal Synchronous Read Cycle Timing Diagram (One Wait State) MOTOROLA MC68302 USER’S MANUAL 6-21...
Page 310: Figure 6-12. External Master Internal Synchronous Write Cycle Timing Diagram
Electrical Characteristics CLKO A23–A1 (INPUT) (INPUT) (OUTPUT) (INPUT) (INPUT) D0–D15 (INPUT) DTACK (OUTPUT) Figure 6-12. External Master Internal Synchronous Write Cycle Timing Diagram 6-22 MC68302 USER’S MANUAL MOTOROLA...
Page 311: Ac Electrical Specifications-Internal Master Internal Read/Write Cycles
— — — CHDOV AS High to Data-Out Hold Time — — — ASHDOH CLKO (OUTPUT) A23-A1 (OUTPUT) (OUTPUT) (OUTPUT) (OUTPUT) (OUTPUT) D15-D0 (OUTPUT) DTACK (OUTPUT) Figure 6-13. Internal Master Internal Read/Write Cycle Timing Diagram MOTOROLA MC68302 USER’S MANUAL 6-23...
Page 312: Ac Electrical Specifications-Chip-Select Timing Internal Master
3.Since AS and CS are asserted/negated on the same CLKO edges, no AS to CS relative timings can be speciﬁed. However, CS timings are given relative to a number of other signals, in the same manner as AS. See Figure 6-2 and Figure 6-3 for diagrams. 6-24 MC68302 USER’S MANUAL MOTOROLA...
Page 313: Ac Electrical Specifications-Chip-Select Timing External Master
1.The minimum value must be met to guarantee write protection operation. 2.This speciﬁcation is valid when the ADCE or WPVE bits in the SCR are set. 3.Also applies after a timeout of the hardware watchdog. MOTOROLA MC68302 USER’S MANUAL 6-25...
Page 314: Ac Electrical Specifications-Parallel I/O
Input Data Setup Time (to Clock Low) — — — Input Data Hold Time (from Clock Low) — — — Clock High to Data-out Valid — — — CHDOV (CPU Writes Data, Control, or Direction) 6-26 MC68302 USER’S MANUAL MOTOROLA...
Page 315: Ac Electrical Specifications-Interrupts
Minimum Time Between Active Edges — — — AEMT NOTE: Setup time for the asynchronous inputs IPL2–IPL0 and AVEC guarantees their recognition at the next falling edge of the clock. (INPUT) Figure 6-17. Interrupts Timing Diagram MOTOROLA MC68302 USER’S MANUAL 6-27...
Page 316: Ac Electrical Specifications-Timers
2. The TIN specs above do not apply to the use of TIN1 as a baud rate generator input clock. In such a case, speciﬁcations 1–3 may be used. CLKO TOUT (OUTPUT) (INPUT) (INPUT) Figure 6-18. Timers Timing Diagram 6-28 MC68302 USER’S MANUAL MOTOROLA...
Page 317: Ac Electrical Specifications-Serial Communications Port
1. This also applies when SPCLK is inverted by CI in the SPMODE register. 2. The enable signals for the slaves may be implemented by the parallel I/O pins. SPCLK (OUTPUT) SPTXD (OUTPUT) SPRXD (INPUT) Figure 6-19. Serial Communication Port Timing Diagram MOTOROLA MC68302 USER’S MANUAL 6-29...
Page 318: Ac Electrical Specifications-Idl Timing
2. High impedance is measured at the 30% and 70% of V points, with the line at V /2 through 10K in parallel with130 pF. 3. Where P = 1/CLKO. Thus, for a 16.67-MHz CLKO rate, P = 60 ns. 6-30 MC68302 USER’S MANUAL MOTOROLA...
Page 319: Figure 6-20. Idl Timing Diagram
Electrical Characteristics Figure 6-20. IDL Timing Diagram MOTOROLA MC68302 USER’S MANUAL 6-31...
Page 320: Ac Electrical Specifications-Gci Timing
2. Condition C L = 150 pF. L1TD becomes valid after the L1CLK rising edge or L1SY1, whichever is later. 3.SDS1–SDS2 become valid after the L1CLK rising edge or L1SY1, whichever is later. 4.Schmitt trigger used on input buffer. 5.Where P = 1/CLKO. Thus, for a 16.67-MHz CLKO rate, P = 60 ns. 6-32 MC68302 USER’S MANUAL MOTOROLA...
Page 321: Figure 6-21. Gci Timing Diagram
Electrical Characteristics Figure 6-21. GCI Timing Diagram MOTOROLA MC68302 USER’S MANUAL 6-33...
Page 322: Ac Electrical Specifications-Pcm Timing
PCM CH-1. Another example is using CH-1 and CH-2 only, where CH-1 and CH-2 are not contiguous on the PCM highway. 3. Speciﬁcation valid for both sync methods. 4. Where P = 1/CLKO. Thus, for a 16.67-MHz CLKO rate, P = 60 ns. 6-34 MC68302 USER’S MANUAL MOTOROLA...
Page 323: Figure 6-22. Pcm Timing Diagram (Sync Envelopes Data)
NOTE: (*) If L1SYn is guaranteed to make a smooth low to high transition (no spikes) while the clock is high, setup time can be defined as shown (min 20 ns). Figure 6-23. PCM Timing Diagram (SYNC Prior to 8-Bit Data) MOTOROLA MC68302 USER’S MANUAL 6-35...
Page 324: Ac Electrical Specifications-Nmsi Timing
2. Also applies to CD hold time when CD is used as an external sync in BISYNC or totally transparent mode. 3. Schmitt triggers used on input buffers. 4. Where P = 1/CLKO. Thus, for a 16.67-MHz CLKO rate, P = 60 ns. 6-36 MC68302 USER’S MANUAL MOTOROLA...
Page 325: Figure 6-24. Nmsi Timing Diagram
Electrical Characteristics Figure 6-24. NMSI Timing Diagram MOTOROLA MC68302 USER’S MANUAL 6-37...
Page 326 Electrical Characteristics 6-38 MC68302 USER’S MANUAL MOTOROLA...
Page 327: Mechanical Data And Ordering Information
V DD TXD1 RTS1 BUSW BRG1 DISCPU V DD DONE DACK BOTTOM VIEW PA12 DREQ TXD3 RCLK3 TCLK3 V DD TXD2 SDS2 RXD3 V DD RXD2 CTS1 TCLK2 V DD RCLK2 RTS2 V DD CTS3 CTS2 RXD1 MOTOROLA MC68302 USER’S MANUAL...
Page 328: Plastic Surface Mount (Pqfp)
7.1.2 Plastic Surface Mount (PQFP) V DD TOUT2 TIN2 TOUT1 V DD TIN1 IACK1 IACK6 IACK7 V DD XTAL EXTAL TOP VIEW V DD CLKO IPL0 IPL1 V DD IPL2 BERR AVEC RESET HALT BGACK BCLR CTS3 DTACK MC68302 USER’S MANUAL MOTOROLA...
Page 329: Thin Surface Mount (Tqfp)
7.1.3 Thin Surface Mount (TQFP) 127 126 TOUT2 TIN2 TOUT1 V CC TIN1 IACK1 IACK6 IACK7 MC68302 XTAL (Top View) EXTAL V CC V CC CLKO IPL0 IPL1 IPL2 BERR AVEC RESET HALT BGACK BCLR DTACK CTS3 MOTOROLA MC68302 USER’S MANUAL...
Page 330: Package Dimensions
Mechanical Data and Ordering Information 7.2 PACKAGE DIMENSIONS 7.2.1 Pin Grid Array (PGA) –T– –X– –A– PIN A–1 –B– 145 PL CASE 768E-01 ISSUE O DATE 04/04/94 MC68302 USER’S MANUAL MOTOROLA...
Page 331: Plastic Surface Mount (Pqfp)
6. DIM S AND V TO BE DETERMINED AT SEATING PLANE, DATUM -T-. 0.51 0.76 0.020 0.030 7. DIM A, B, N AND R TO BE DETERMINED AT DATUM PLANE -W-. 27.88 28.01 1.097 1.103 28.01 1.103 27.88 1.097 1.085 27.31 27.55 1.075 27.31 27.55 1.075 1.085 MOTOROLA MC68302 USER’S MANUAL...
Page 332: Thin Surface Mount (Tqfp)
DETAIL "C" 11.00 BSC 0.433 BSC 22.00 BSC 0.866 BSC 11.00 BSC 0.433 BSC 0.25 REF 0.010 REF 0.039 REF 1.00 REF 0.09 0.16 0.004 0.006 0° 0° 7° 0° 0° 7° 11° 13° 11° 13° MC68302 USER’S MANUAL MOTOROLA...
Page 333: Ordering Information
- 40 C to + 85 C MC68302CFC20 0 C to 70 C MC68302FC25 16.67 0 C to 70 C MC68302PV16 Thin Surface Mount 0 C to 70 C MC68302PV20 (PV Suffix) 16.67 0 C to 70 C MC68302PV16V MOTOROLA MC68302 USER’S MANUAL...
Page 334 Mechanical Data and Ordering Information MC68302 USER’S MANUAL MOTOROLA...
Page 335: Appendix Ascc Performance
Some users may wish to tolerate an occasional underrun/overrun to slightly increase performance. For example, a ratio of 1:10 in the following table shows that an MC68302 system clock of 16.67 MHz can support an MC68302 serial rate of 1.67 Mbps. Typically, this 1.67-Mbps rate would be achieved with 1 bit every 1.67-MHz serial clock.
Page 336 4. The last address or control character in the table was checked. 5. For the DDCMP, the frame length was 6 and 59 bytes for the two BDs. 6. When the performance of a high-speed channel together with a low-speed channel was measured, the high-speed MC68302 USER’S MANUAL MOTOROLA...
Page 337 2x better. Since operation at very high data rates is characteristic of HDLC-framed channels rather than BISYNC-, DDCMP-, or async-framed channels, the user can also use the MC68302 in conjunction with either the Motorola MC68605 1984 CCITT X.25 LAPB controller, the MC68606 CCITT Q.921 multilink LAPD controller, or the MC145488 dual data link control-...
Page 338 SCC Performance MC68302 USER’S MANUAL MOTOROLA...
Page 339: Development Tools And Support
These are in the form of binary relocatable object code as well as source code written in C. • Portability All of the modules may be ported to different MC68302 implementations and combined with user-developed code. Well-defined software interface documentation is available for all provided modules.
Page 340 (see Figure B-1). The chip driver module features are as follows: • All software modules use the driver module as their interface to the MC68302 • Illustrates initialization of the MC68302 and interrupt handling •...
Page 341: Figure B-1. Software Overview
OF INTERMODULE COMMUNICATION LAPD MODULE LAPB MODULE USER-SUPPLIED USER-SUPPLIED MODULES CAN BE INTEGRATED AT ANY LEVEL LAYER 2 DRIVER MODULE THE MC68302 DOES SOME ACCESS TO THE LAYER 2 FUNCTIONS (E.G. MC68302 IS MADE ADDRESS RECOGNITION) THROUGH THE DRIVER MC68302 LAYER 1 DEVICE Figure B-1.
Page 342 LAPB link • Special mode for internal loopback (frames are not sent to the driver) • Supports external loopback between two MC68302 serial channels or on the same MC68302 serial channel • Trace option for reporting to system management each primitive issued by the LAPB module to layer 3 or to layer 2 management The X.25 module features are as follows:...
Page 343 IMP) or to issue specific commands. The commands may result in specific IMP com- mands or in the execution of protocol-defined primitives in one of the protocol modules. The chip driver module is available in C source code form. The source code requires no li- cense. MOTOROLA MC68302 USER’S MANUAL...
Page 344: Third-Party Software Support
B.5 302 FAMILY ADS SYSTEM The M68302FADS is an integrated Family Applications Development System (FADS) de- signed to aid hardware and software developers of the MC68302, MC68LC302, MC68PM302, and MC68EN302 in quickly evaluating and developing applications for these devices. All of the hardware resources needed to download and debug application software...
Page 345 —68000 bus signals brought out to logic analyzer connectors. —Single +5Vdc power supply with onboard 5V to +/-12Volt converter. • IMP(68302) Support Features Included —MC68302 at 25 MHz —MC68LC302 at 20 MHz —MC68PM302 at 20 MHz. —512 kbyte, zero wait state static RAM, expandable up to 1 Mbyte. (16 bit orientation) —1 Mbyte FLASH.
Page 346: Figure B-2. Mc68302Fads
PORT PORT PORT PCMCIA 68000 68302 68LC302 68PM302 EXTENDER FLASH AND CARD IMP EXPANSION CONN. EXPANSION CONN. LOGIC ANALYZER FOR IMP CODE AND BUS ANALYSIS ANALYZER CABLE LOGIC ANALYZER FOR PERIPHERAL BUS ANALYSIS Figure B-2. MC68302FADS MC68302 USER’S MANUAL MOTOROLA...
Page 347: Risc Microcode From Ram
APPENDIX C RISC MICROCODE FROM RAM The MC68302 RISC processor has an option to execute microcode from the 576-byte user RAM in the on-chip dual-port RAM. In this mode, the 576-byte user RAM cannot be access- ed by the M68000 core or other M68000 bus masters. Also in this mode, port A pins are op- tionally available to the RlSC processor as well as the M68000 core.
Page 348: Ss7 Protocol Support
Any or all three SCCs can become an SS7 protocol controller. The SS7 microcode increas- es that portion of layer 2 SS7 already supported by the HDLC features in the MC68302. This implementation of SS7, however, is not a complete layer 2 implementation. Rather, the ad-...
Page 349: Centronics Reception Controller
The package allows a UART to automatically detect the baud rate of a serial stream and ad- just to it. This is useful in modem applications that must support an autobaud capability. It is Centronics is a trademark of Centronics. MOTOROLA MC68302 USER’S MANUAL...
Page 350: Microcode From Ram Initialization Sequence
38.4K, 57.6K, 64K, 96K, and 115.2K. To estimate the performance of the AutoBaud micro- code package, the performance table in Appendix A of the MC68302 user’s manual can be used. The maximum full-duplex rate for a BISYNC channel is one-tenth of the system clock rate.
Page 351: Mc68302 Applications
BUSW is pulled high for 16-bit operation and may not be modified dynamically. Choice of 8- bit operation could be used to eliminate two of the memory chips. BERR is pulled high since it is an open-drain signal. It will be asserted low by the MC68302 if the hardware watchdog terminates a stalled bus cycle.
Page 352: Figure D-1. Mc68302 Minimum System Configuration (Sheet 1 Of
BGACK DTACK DISCPU BCLR 1.2K 4.7K 5V 5V 5V LS05 HALT IPL0 IPL1 RESET IPL2 LS05 POWER-ON RESET 1N4001 MC1455 0.1 F 0.1 F 0.47 F Figure D-1. MC68302 Minimum System Configuration (Sheet 1 of 2) MC68302 USER’S MANUAL MOTOROLA...
Page 353: Reset Circuit
The reset circuit shown uses an MC1455 timer to generate a 0.5-sec pulse until DlS reaches the 2/3 V threshold level. After that, DIS discharges the 0.47- F capacitor. When DIS falls below 2/3 V , then the output pin (O) is pulled low, ending the reset to the MC68302. This MOTOROLA MC68302 USER’S MANUAL...
Page 354: Memory Interface
The time between CS low and data valid must be calculated for proper timing of read cycles. This time is approximately 2 1/2 clocks. CS is asserted by the MC68302 after the rising edge of S2. Data must be valid a setup time before the S6 falling edge. Thus, for a 16.67-MHz device, the equation for the time between CS low and data valid is as follows: MC68302 USER’S MANUAL...
Page 355: Switching The External Rom And Ram Using The Mc68302
For proper timing of write cycles, it is important to know how much time elapses between CS negated and the data out hold time. With a 16.67-MHz MC68302, this value is a 10-ns minimum. Thus, on a CS-controlled RAM write cycle, the RAM required data hold time must be <= 10 ns.
Page 356: Switching Process
The following situation now exists: ROM—$0 to $03FFFF RAM—$400000 to $40FFFF MC68302—$700000 to $700FFF D.2.3 Switching Process To perform the switch, jump from the ROM to the dual-port RAM, reconfigure chip selects 1 and 0, and then jump back to the ROM. It is important that the RAM be moved first to ensure that an exception vector table is always present.
Page 357: Mc68302 Buffer Processing And Interrupt Handling
In the MC68302, up to 8 receive BDs and 8 transmit BDs can be defined per SCC. These BDs are stored in predefined places in the MC68302 dual-port RAM. The “wrap” bit is set in the last BD, causing the SCC to wrap back around to the first BD when processing of the last BD is complete.
Page 358: Figure D-4. Transmit And Receive Bd Tables
(or which one it will be using next). TBD# and RBD# always sequence around the queue of BDs in a circular fashion and are initialized to the first BD as shown. D.3.2 MC68302 Buffer Processing The communications processor (CP) processes the transmit BDs in a straightforward fash- ion.
Page 359: New Pointers
Confirm transmit data (CTD) shows the next transmit BD that will be confirmed. To confirm a buffer, check for errors after transmission and then mark the BD as available for USQ. This is the last pointer to move in the transmit process. MOTOROLA MC68302 USER’S MANUAL...
Page 360: Initial Conditions
The user may or may not want to analyze data in the buffer at this time. c. Move data out of buffer or change the BD pointer to a new location. d. Clear out the data length field so that it is zero to start with. D-10 MC68302 USER’S MANUAL MOTOROLA...
Page 361: Final Comments
;Interrupt Vector for SCC1 * Commonly used Registers and Parameters $0F2 ;Base Address Register $0F4 ;System Control Register CKCR $0F6 ;Clock Control Register GIMR BASE + $812 ;Global Interrupt Mode Register BASE + $814 ;Interrupt Pending Register MOTOROLA MC68302 USER’S MANUAL D-11...
Page 362 #0,SCR ;Nothing special for this example ***Setups for interrupt *** MOVE.W #$0A0,GIMR ;Normal mode, v7–v5 = 5 MOVE.W #0,IMR ;Mask off all for now MOVE.W #$FFFF,IPR ;Clear IPR *** Set up Serial Interface Connection *** D-12 MC68302 USER’S MANUAL MOTOROLA...
Page 363 ;A1 points to the first buffer MOVE.W #$D000,D1 ;D1 is used for setting the status of BD ;Empty = 1, External = 1, Int=1 MOVE.W #$F000,D2 ;D2 is for the last BD, Wrap = 1 MOTOROLA MC68302 USER’S MANUAL D-13...
Page 364 ;D1 is used to count the BD SUBO.B #1,D1 NxtBF CLR.L ;D2 is used as content and counter of BF NxtBT MOVE.B D2,(A0)+ ADDQ.B #$1,D2 CMPI.B #SZ_BF,D2 ;Number of data in a buffer is 16 D-14 MC68302 USER’S MANUAL MOTOROLA...
Page 365 D1,D2 ;SCCE1 , D2 ANDI.W #9,D2 ;Are RXF or RXB set? CMPI.W #0,D2 ;If they are set BNE.B RX_INT ;Handle receiver's interrupt CK_TX MOVE.L D1,D2 ;SCCE1 , D2 ANDI.W #$12,D2 ;Are TXF or TXB set? MOTOROLA MC68302 USER’S MANUAL D-15...
Page 366 ;data length = 0 ***Check status in TXBD for erratic events *** * If status bits are all 0 then continue, else SHUTDOWN the confirming * process. This in turn shuts down the whole program, since soon D-16 MC68302 USER’S MANUAL MOTOROLA...
Page 367: Configuring A Uart On The Mc68302
The following paragraphs discuss a working example of software that configures the MC68302 SCC3 for the UART mode. The code receives data from the UART receiver on a character-by-character basis and retransmits it out of the UART transmitter. The code, which runs as is on the ADS302 board, is an excellent starting point for understanding how to program the UART mode or to create a simple UART handler to support a debug monitor.
Page 368: Organization Of Buffers
D.4.2 Organization of Buffers In the MC68302, there is no such thing as an receive register (Rx) or transmit register (Tx). Rather, a flexible structure called a buffer descriptor (BD) is used. In this example, two Rx BDs and two Tx BDs are used.
Page 369: Assumptions About The System
BDs in software. D.4.3 Assumptions about the System The code, which was run on the ADS302 board, assumes that the MC68302 peripherals are placed at the default position of $700000 (i.e., BAR is written with $700). It also assumes that SCC3 is used.
Page 370 *S CC3 I ni ti a li z at i o n C o de $30300 MOVE.W #$700.BAR ;BAR = 0700 * Base Address - S700000, so ALL MC68302 on-chip peripherals begin at * address S700xxx. MOVE.W #$00A0, GIMR ;GIMR = 00a0 MOVE.W...
Page 371 ; Move char from Rx Buffer to Tx Buffer ADDQ.W #2,A2 ; Increment A2 to point to byte count MOVE.W #$1,(A2) ; Set TxBD Byte count to 1 SUBO.W #2,A2 ; A2 now points to beginning of Tx BD MOTOROLA MC68302 USER’S MANUAL D-21...
Page 372 ;Inc A0 to point to Rx BD byte status CMPI.B #$0,(A0) ;Does status = 00? BNE.B BSTAT ;Jump to Bad Status it not 00 INCPTR SUBQ.W #1,A0 ;Dec A0 to point to beginning of Rx BD ANDI.W #$FF00,(A0) ;Clear out Rx BD status D-22 MC68302 USER’S MANUAL MOTOROLA...
Page 373: Idma Overview
(DMA) controller is used. The MC68302 contains an independent direct memory access (IDMA) controller. Engineers developing system architectures requir- ing both the M68000 microprocessor and DMA can use the MC68302 to obtain both building blocks in one package.
Page 374: Idma Software Initialization
(DAPR). The byte count register (BCR) specifies the number of bytes to be transferred and is decremented once for each byte transferred. Note that the six SDMA channels on the MC68302 have a higher priority than the IDMA (unless the IDMA is perform- ing a maximum rate burst).
Page 375: Table D-2. Channel Mode Register Bits
2. The DONE bit is set in the CSR at the conclusion of data transfer. 3. Transfer occurs at maximum rate. Hardware signal DREQ is level sensitive. 4. Hardware signal DREQ is edge sensitive. 5. These percentages are valid only when bits 11 and 10 = 00. MOTOROLA MC68302 USER’S MANUAL D-25...
Page 376: External Cycles Examples
MC68302 Applications D.5.6 External Cycles Examples If the MC68302 is the current bus master and no other internal or external resources are ar- bitrating for the bus, then the IDMA will obtain bus mastership and perform the data move- ment cycles when the DREQ signal meets the asynchronous setup time prior to the falling edge of clock.
Page 377: Figure D-7. Typical Idma External Cycles (Normal Operation)
Figure D-8 shows the peripheral terminating the current IDMA transfer. Note that the DONE signal has been asserted by the peripheral. The IDMA will indicate the transfer has been completed by setting bits in the CSR (see Table D-3). MOTOROLA MC68302 USER’S MANUAL D-27...
Page 378: Figure D-8. Typical Idma External Cycles Showing Block Transfer Termination
16-bit bus. This type of transfer duplicates the function of an M68000 MOVEP instruction. READ 1 READ 2 WRITE CLKO (OUTPUT) DTACK DACK (OUTPUT) BGACK Figure D-9. Typical IDMA Source to Word Destination IDMA Cycles D-28 MC68302 USER’S MANUAL MOTOROLA...
Page 379: Figure D-10. Burst Mode Cycles
(bit 11) in the IMR and 2) setting one or both interrupt enable (INTN and INTE) bits in the CMR (see Table D-1). Once in the interrupt handler, four bits in the CSR indicate the reason for termination of an IDMA data block (see Table D-2). MOTOROLA MC68302 USER’S MANUAL D-29...
Page 380: Final Notes
D.6 MC68302 MULTIPROTOCOL CONTROLLER TIED TO IDL BUS FORMS AND ISDN VOICE/DATA TERMINAL The following paragraphs discuss how the MC68302 can be tied to the interchip digital link (IDL) bus, which enables connectivity to a family of ISDN chips. The IDL bus connects the MC68302 integrated controller with the MC145475 S/T interface and the MC145554 CO- DEC to form a basic rate ISDN voice/data terminal (see Figure D-11).
Page 381: M68000 Core
MC68302 Applications D.6.1 M68000 Core The M68000 core processor on the MC68302 is instruction and timing compatible with the standard MC68000 (16-bit) or MC68008 (8-bit) versions of the M68000 Family. The core supports bus lock during read-modify-write cycles, a low latency interrupt mechanism, and bus width configuration.
Page 382: Figure D-12. Idl Bus Boundaries
ISDN TELEPHONE IDL BUS BOUNDARIES Figure D-12. IDL Bus Boundaries Motorola offers a full line of ISDN/IDL compatible chips that enable modular and portable design of ISDN equipment: • MC145472 — ISDN U interface transceiver conforms to the American Standard for ISDN basic access.
Page 383: Figure D-13. Idl Frame Structure
• RXDATA — the input line that receives data from the TXDATA of another part. D.6.6 IMP/IDL Interconnection The MC68302 directly connects to the IDL bus with no glue logic. The MC68302 is an IDL slave (accepts IDL timing from the bus). In the application described, the IDL master device is the MC145475 S/T interface chip (see Figure D-14).
Page 384: Figure D-14. Idl Bus To Other Slaves
DGRT. In case of a collision, DGRT will be negated, signaling that D-channel transmission must be aborted. If the MC68302 is programmed to do so, an automatic retransmission will take place when the D-channel is available again. The MC68302 generates two serial data strobe signals, SDS1 and SDS2, which are pro- grammed to envelope the B1 or/and B2 time slots.
Page 385: Figure D-15. Serial Interface Configuration
D.6.7 Serial Interface Configuration To allow the MC68302 to be tied to the IDL bus, the serial interface (see Figure D-15) must be configured to the IDL mode. A value of $0C76 written to the SIMR will set the following...
Page 386: Scc Configuration
NOTE In addition to programming the SCCs registers, the protocol- specific parameter RAM of each SCC should be initialized by the control software according to the protocol selected. D-36 MC68302 USER’S MANUAL MOTOROLA...
Page 387: Parallel L/O Port A Configuration
The SCP is a four-wire bus consisting of transmit path, receive path, associated clock, and enable signal (see Figure D-16). The clock determines the rate of the exchange of data in both the transmit and receive directions, and the enable signal governs when this exchange occurs. MOTOROLA MC68302 USER’S MANUAL D-37...
Page 388: Scp Configuration
The interconnection between the MC68302 SCP and the MC145475 is straightforward. The MC68302 is an SCP master device and will generate the clock timing and the SCP_ENABLE for the SCP transaction. The SCP_EN signal is driven by a parallel output pin and must be handled by software (asserted for each transaction between the MC68302 and the MC145475).
Page 389: Additional Imp To S/T Chip Connections
T chip to the MC68302 (see Figure D-17). IRQ —The active-low signal sends an interrupt request from the MC145475 to the MC68302 core. This is an active-low signal that is asserted when one or more of the fol- lowing events occurs: —...
Page 390: Figure D-17. Discrete Signal Interconnection
S/T chip after power-up. Nibble register 2 allows activation (TE/NT) and deactivation (NT) of the S/T loop. To activate the loop, write $8 to NR2. To deacti- vate the loop, write $4 to NR2. D-40 MC68302 USER’S MANUAL MOTOROLA...
Page 391: Figure D-18. Codec/Idl Electrical Connection
PCM systems. The MC145554 is a Mu-law device that can be tied directly to the IDL bus. The SDS strobe generated by the MC68302 serial interface can be used to route the CODEC to the proper B-channel.
Page 392: Figure D-19. Typical Slave Mode Example
A typical slave mode ex- ample is shown in Figure D-19. A single master MC68302 (i.e., one with the M68000 core enabled) can access and control one or more slave MC68302s. (i.e., ones with the M68000 core disabled.)
Page 393: Synchronous Vs. Asynchronous Accesses
MC68302 activity. If the SAM bit in the SCR is set, the following accesses to the slave MC68302 will be syn- chronous. Writes will be zero wait states, and reads can be either zero or one wait state, based on the EMWS bit in the SCR.
Page 394: Dealing With Interrupts
The external decoding and address buffer logic required to do this slows down the interface timing (and adds expense). Rather, the VGE bit is intended for applications where a single MC68302 is a slave to an- other processor such as the MC68020.
Page 395: Final Notes
A 1k resistor may be required in this case as well. However, if the master MC68302 chip-select logic is used by the slave, the chip-select comparison for the A23 pin can be disabled. (If this trick is used, it is important that no peripherals or memory be mapped to the chip select's corresponding area in the upper half of system memory).
Page 396: Figure D-20. Dual Master-Slave System
— for example, voice data. There is no reason to encode voice data, and no error correction is needed. With voice data, an occasional dropped bit will not interfere with the data stream in any significant way. The MC68302 transparent mode works well for this type of applica- tion.
Page 397: Physical Interface To Accompany Transparent Mode
MC68302 Applications SCCs on the MC68302 can do this very efficiently because of their sophisticated DMA ca- pability, and very little MC68000 core intervention is required. Third, some applications require the switching of data without interfering with the protocol encoding itself. For instance, in a multiplexer, data from a high-speed time-multiplexed serial stream is multiplexed into multiple low-speed data streams.
Page 398: Figure D-21. Nmsi Pin Definitions
64 kbps B channels and on the one 16 kbps D channel in basic rate ISDN. If you are not interfacing to a 2B + D ISDN environment, you can probably rule out using IDL and GCI. D-48 MC68302 USER’S MANUAL MOTOROLA...
Page 399: Figure D-22. Multiplexed Modes Example
NMSI or all but one as NMSI. Thus, you can choose from the following four combinations: 1. NMSI1, NMSI2, and NMSI3 2. PCM, NMSI2, and NMSI3 3. IDL, NMSI2, and NMSI3 4. GCI, NMSI2, and NMSI3 MOTOROLA MC68302 USER’S MANUAL D-49...
Page 400: General Transparent Mode Behavior
2. GCI using SCC1 and (either SCC2 or SCC3 or both) NOTE The preceding four examples of physical interface combinations apply equally well to other MC68302-supported protocols such as HDLC. Since the purposes of GCI and IDL are clear, the real challenge is choosing between NMSI and PCM.
Page 401 Rx BD, the RX event in the SCCE register will be set. Also, whenever a word of data is written to the receive buffer, the RCH bit is set in the SCCE. MOTOROLA MC68302 USER’S MANUAL D-51...
Page 402: Transparent Mode With The Nmsi Physical Interface
CTS lost error is indicated in the transmit buffer descriptor (Tx BD). On the receiving side, the CD signal going low tells the MC68302 to gate data into this SCC. Once low, CD should remain low for the entire frame, or reception is terminated and a CD lost error is signaled in the receive buffer descriptor (Rx BD).
Page 403: Figure D-23. Simplest Transmit Case In Nmsi
DATA BITS ARE SAMPLED AT EVERY RISING EDGE OF RCLK CD (SYNC) (INPUT) NO BYTE ALIGNMENT PERFORMED ON RECEIVE EXSYN = 1 NTSYN = 1 DIAG1-DIAG0 BITS = 11 Figure D-24. Simplest Receive Case in NMSI MOTOROLA MC68302 USER’S MANUAL D-53...
Page 404: Figure D-25. Using Cts In The Nmsi Transmit Case
6.5 TCLKs. Notice that the rising edge of CD (sync) and subsequent falling edges of CD (sync) (not shown) have no effect, since synchro- nization has already been achieved. D-54 MC68302 USER’S MANUAL MOTOROLA...
Page 405: Figure D-26. Using Cd (Sync) In The Nmsi Transmit Case
SCC really are separate and distinct; however, in transparent mode, the receive and transmit halves of the SCC share the CD (sync) pin, which is not true in normal NMSI. MOTOROLA MC68302 USER’S MANUAL D-55...
Page 406: Figure D-27. Using Cd (Sync) In The Nmsi Receive Case
Normal BISYNC mode has the advantage of being able to store an odd number of bytes in the receive buffer, rather than words. A disadvantage, however, is lower serial performance. D-56 MC68302 USER’S MANUAL MOTOROLA...
Page 407 Refer to 4.5.7 SCC Initialization for the proper order. Other registers, such as MRBLR, RFCR, TFCR, SCCM, IMR, and SIMODE, still have to be defined, but their values are of no particular relevance to the loopback operation. MOTOROLA MC68302 USER’S MANUAL D-57...
Page 408: Transync Mode
The gating of clocks can provide extra control over the transmission and reception of data, albeit with extra logic external to the MC68302. The SCCs are designed with static logic; thus, the clock signal may be held in a constant high/low state for any period of time. When-...
Page 409 The ENTER HUNT MODE command should be given between the 9th and 16th se- rial clock, after the last bit of the frame has been clocked into the MC68302 and at least three serial clocks before the next CD (sync). Serial clocks do not need to be running while this command is executed.
Page 410: Using Transparent Mode With Pcm Highway Mode
Notice that there is only one clock signal for PCM highway. This clock functions as both a receive and transmit clock. Thus, if receive data needs to be clocked into the MC68302 at a different time or speed than transmit data is being clocked out, then PCM highway is not an appropriate interface and NMSI should be used instead.
Page 411: Figure D-29. Routing Channels In Pcm Envelope Mode
PCM mode gives greater control over what intervals transparent data can be transmitted and received. However, in PCM mode, the clocks are gated by the physical interface on the MC68302 as opposed to external hardware. MOTOROLA MC68302 USER’S MANUAL...
Page 412 2. Clear ENT. 3. Give RESTART TRANSMIT command. 4. Set ready bit of next Tx BD to transmit. 5. Generate interrupt to MC68302 on falling L1SY1 /L1SY0 pin. 6. Now that time slot is inactive, set ENT bit. D-62 MC68302 USER’S MANUAL...
Page 413: Figure D-30. Pcm Transmission Timing Technique
ENT bit should at least guarantee a fixed delay to the start of data. In this case, there will be additional time slots with $FF data until the data1 byte is transmitted. MOTOROLA MC68302 USER’S MANUAL D-63...
Page 414: Pcm Mode Final Thoughts
GCI/IDL frame and if ready bit of the Tx BD is set at a consistent time relative to the GCI/IDL frame (preferably before the ENT bit is set), a consistent starting point of byte alignment (either B1 or B2) can be obtained. If data is then transmitted in a continuous D-64 MC68302 USER’S MANUAL MOTOROLA...
Page 415: Initializing Transparent Mode
Full examples of the assembler code required to initialize the HDLC and UART protocols are given in D.3 MC68302 Buffer Processing and Interrupt Handling and D.4 Configuring A Uart on the MC68302. A transparent mode initialization follows the same flow as these subsec- tions except that different values would be used.
Page 416 If it was ready, it would be filled with all $FFs (idles) after the first two buffers were filled. Rx BD = $D000 $0000 $0004 $0000 Rx BD = $D000 $0000 $0004 $0010 D-66 MC68302 USER’S MANUAL MOTOROLA...
Page 417: Special Uses Of Transparent Mode
D.8.12 Special Uses of Transparent Mode The following paragraphs discuss two special cases where transparent mode can be used to extend the capabilities of the MC68302 UART mode. D.8.12.1 5- OR 6-BIT UART. One special protocol of note that can be accomplished with transparent mode is the building of a 5- or 6-bit UART.
Page 418: Scp As A Transparent Mode Alternative
SCP must be able to accept an external input clock. It is possible for the SCP to interface externally to one of the MC68302's SCCs. For instance, this type interface could be used to convert HDLC-encoded data from a serial format to a parallel format so that it can be moved over the M68000 bus.
Page 419: Figure D-31. Scp Timing
The following paragraphs describe a hardware design that uses the MC68195 LocalTalk Adaptor (LA) to interface the MC68302 to AppleTalk. The LA is designed to work directly with the MC68302 for this purpose. The design is also suitable to those wishing to build a proprietary HDLC-based LAN.
Page 420: Overview Of The Board
Note that there is a pullup on the SCC2 RTS2 pin because SCC2 on the MC68302, unlike SCC1, has its pins multiplexed with parallel l/O pins. These pins default to the input state upon reset.
Page 421: Figure D-32. Local Talk Adaptor Board
GND,V ,MODE 16 RESET 15 F 5,8,4 14 CLK 12 XTAL0 35 CHEN1 15pF 37 CHEN2 15pF 10,15,21,43 V 11 XTAL1 2.304 MHz GND A1 150pF 2,7,13,24 GND GND B1 Figure D-32. Local Talk Adaptor Board MOTOROLA MC68302 USER’S MANUAL D-71...
Page 422 MC68302 Applications D-72 MC68302 USER’S MANUAL MOTOROLA...
Page 423: Scc Programming Reference
Table E-1 (b). depicts the general and protocol-specific parameter RAM for each SCC. The SCC registers are shown in Table E-1 (c), and the communications processor registers are shown in Table E-1 (d). Note that reserved bits in registers should be written as zeros. MOTOROLA MC68360 USER’S MANUAL...
Page 424: Table E-1 (B). Hdlc Programming Model (Continued) General Parameter And Hdlc Protocol-Specific Ram For Sccx
Rx BD 7 Data Pointer (Low Word) Tx BD 7 Data Pointer (Low Word) NOTE: The offset is from the MC68302 base address + ($400 for SCC1, $500 for SCC2, or $600 for SCC3). Table E-1 (b). HDLC Programming Model (Continued)
Page 425: Communications Processor (Cp) Registers
Mask Register (SCCM) Reserved Status Register (SCCS) Reserved Reserved NOTE: The offset is from the MC68302 base address + ($880 for SCC1, $890 for SCC2, or $8A0 for SCC3). Table E-1 (d).General Registers (Only One Set) Initialized Offset Name by User...
Page 426: E.1.1.1.2 Serial Interface Mode Register (Simode)
0 = One pulse wide prior to the 8-bit data. 1 = N pulses wide and envelopes the N-bit data. SDIAG1, SDIAG0—Serial Interface Diagnostic Mode 00 = Normal operation. 01 = Automatic echo. 10 = Internal loopback. 11 = Loopback control. MC68360 USER’S MANUAL MOTOROLA...
Page 427: E.1.1.1.3 Serial Interface Mask Register (Simask)
$8B2. The SIMASK register is used to configure which bits on the B1 and B2 channels are used in the GCI and IDL modes. Bit 0 of SIMASK is the first bit transmitted and received on B1. MOTOROLA MC68360 USER’S MANUAL...
Page 428: E.1.1.2 Per Scc Registers
(SCC1), $894 (SCC2), and $8A4 (SCC3). The SCM register configures the operation of the SCC and defines HDLC specific parameters. Note that reserved bits in registers should be written as zeros. NOF3 NOF2 NOF1 NOF0 — DIAG1 DIAG0 MODE1 M0DE0 MC68360 USER’S MANUAL MOTOROLA...
Page 429 ENT—Enable Transmitter 0 = Transmitter is disabled. 1 = Transmitter is enabled. MODE1, MODE0—Channel Mode 00 = HDLC. 01 = Asynchronous (UART and DDCMP). 10 = Synchronous DDCMP and V.110. 11 = BISYNC and Promiscuous (Transparent). MOTOROLA MC68360 USER’S MANUAL...
Page 430: E.1.1.2.3 Scc Data Synchronization Register (Dsr)
1 = A frame was received and discarded due to lack of buffers. TXB—Tx Buffer 0 = No interrupt. 1 = A buffer has been transmitted on the HDLC channel (set only if the I bit in the Tx buffer descriptor is set). MC68360 USER’S MANUAL MOTOROLA...
Page 431: E.1.1.2.5 Hdlc Mask Register (Sccm)
E.1.1.3.1 RFCR/TFCR—Rx Function Code/Tx Function Code. This 16-bit parameter contains the function codes of the receive data buffers and transmit data buffers. The user must initialize the function codes (FC2-FC0) to a value less than 7. MOTOROLA MC68360 USER’S MANUAL...
Page 432: Crcec-Crc Error Counter
Each buffer descriptor consists of four words as shown below. Reserved bits in regis- ters should be written as zeros. OFFSET + 0 — — — — OFFSET +2 DATA LENGTH OFFSET +4 RX BUFFER POINTER OFFSET +6 E-10 MC68360 USER’S MANUAL MOTOROLA...
Page 433: E.1.1.4.1 Receive Bd Control/Status Word
0 = An octet aligned frame was received. 1 = A nonoctet aligned frame was received. AB—Rx Abort Sequence 0 = No abort was received. 1 = A minimum of seven ones was received during frame reception. MOTOROLA MC68360 USER’S MANUAL E-11...
Page 434: E.1.1.4.2 Receive Buffer Data Length
1 = The data buffer associated with this BD is in external memory. W—Wrap (final BD in table) 0 = This is not the last BD in the transmit BD table. 1 = This is the last BD in the transmit BD table. E-12 MC68360 USER’S MANUAL MOTOROLA...
Page 435: E.1.1.5.2 Transmit Buffer Data Length
SCC3 serial interface pins as peripheral pins, if SCC2 or SCC3 is used. 2. Write SIMODE to configure the SCCs physical interface. 3. Write SIMASK if IDL or GCI multiplexed mode was selected in SIMODE. E.1.2.2 GENERAL AND HDLC PROTOCOL-SPECIFIC RAM INITIALIZATION. 4. Write RFCR/TFCR. MOTOROLA MC68360 USER’S MANUAL E-13...
Page 436: E.1.2.3 Scc Initialization
2. Clear any unmasked bits that will be used in this interrupt routine. 3. Handle the interrupt events as required by the system. 4. Clear the appropriate SCC bit in the in-service register (ISR) of the interrupt controller. 5. Return from the interrupt. E-14 MC68360 USER’S MANUAL MOTOROLA...
Page 437: E.2 Uart Programming Reference Section
Tx BD 7 Data Pointer (High Word) Rx BD 7 Data Pointer (Low Word) Tx BD 7 Data Pointer (Low Word) NOTE: The offset is from the MC68302 base address + ($400 for SCC1, $500 for SCC2, or $600 for SCC3). MOTOROLA MC68360 USER’S MANUAL...
Page 438 Temporary Receive IDLE Counter Control Character 7 Break Counter Register Control Character 8 NOTE: The offset is from the MC68302 base address + ($400 for SCC1, $500 for SCC2, or $600 for SCC3). Table E-1 (c). SCCx Register Set Initialized Offset...
Page 439: E.2.1.1 Communications Processor (Cp) Registers
0 = CP is ready to receive a new command (should be checked before issuing the next command to the CP). 1 = Command register contains a command to be executed or one that is currently be- ing executed. MOTOROLA MC68360 USER’S MANUAL E-17...
Page 440: E.2.1.1.2 Serial Lnterface Mode Register (Slmode)
B1 RB, B1 RA—B1 Channel Route in IDL/GCI Mode or CH-2 Route in PCM Mode 00 = Channel not supported. 01 = Route channel to SCC1. 10 = Route channel to SCC2 (if MSC2 is cleared). 11 = Route channel to SCC3 (if MSC3 is cleared). E-18 MC68360 USER’S MANUAL MOTOROLA...
Page 441: E.2.1.1.3 Serial Interface Mask Register (Simask)
SCC. WOMS EXTC CD10 DIV4 WOMS—Wired-OR Mode Select 0 = TXD driver operates normally. 1 = TXD driver functions as an open-drain output and may be wired together with other TXD pins. MOTOROLA MC68360 USER’S MANUAL E-19...
Page 442: E.2.1.2.2 Scc Mode Register (Scm)
11 = Force high parity; always send a one in the parity bit position. RPM—Receiver Parity Mode 0 = Odd parity. 1 = Even parity. PEN—Parity Enable 0 = No parity. 1 = Parity is enabled for the transmitter and receiver. E-20 MC68360 USER’S MANUAL MOTOROLA...
Page 443 ENT—Enable Transmitter 0 = Transmitter is disabled. 1 = Transmitter is enabled. MODE1, MODE0—Channel Mode 00 = HDLC. 01 = Asynchronous (UART and DDCMP). 10 = Synchronous DDCMP and V.110. 11 = BISYNC and Promiscuous (Transparent). MOTOROLA MC68360 USER’S MANUAL E-21...
Page 444: E.2.1.2.3 Scc Data Synchronization Register (Dsr)
1 = Control character received (with reject (R) character = 1) and stored in the receive control character register (RCCR). BSY—Busy Condition 0 = No interrupt. 1 = A character was received and discarded due to lack of buffers. E-22 MC68360 USER’S MANUAL MOTOROLA...
Page 445: E.2.1.2.5 Uart Mask Register (Sccm)
The last 18 words are specific to the pro- tocol selected. The following sections discuss the parameters that the user must initialize to configure the UART operation. MOTOROLA MC68360 USER’S MANUAL E-23...
Page 446: E.2.1.3.1 Rfcr/Tfcr—Rx Function Code/Tx Function Code
— — — — — — CHARACTER3 — — — — — — CHARACTER4 — — — — — — CHARACTER5 — — — — — — CHARACTER6 — — — — — — CHARACTER7 E-24 MC68360 USER’S MANUAL MOTOROLA...
Page 447: E.2.1.4 Receive Buffer Descriptors
1 = Address bit of one will be transmitted if a multidrop mode is chosen. E.2.1.4 RECEIVE BUFFER DESCRIPTORS. Each SCC has eight receive buffer descrip- tors. Each buffer descriptor consists of four words as shown below. Reserved bits in regis- ters should be written as zeros. MOTOROLA MC68360 USER’S MANUAL E-25...
Page 448: E.2.1.4.1 Receive Bd Control/Status Word
1 = The address byte matched UADDR1. ID—IDLE Reception 0 = Buffer not closed due to reception of maximum number of IDLE characters (MAX_IDL). 1 = Buffer closed due to reception of maximum number of IDLE characters (MAX_IDL). E-26 MC68360 USER’S MANUAL MOTOROLA...
Page 449: Receive Buffer Data Length
0 = This data buffer is not currently ready for transmission. 1 = This data buffer has been prepared by the user for transmission but has not yet been fully transmitted. Must be set by the user to enable transmission of the buffer. MOTOROLA MC68360 USER’S MANUAL E-27...
Page 450: E.2.1.5.2 Transmit Buffer Data Length
SCC for transmission and reception. The algorithm is not specific and assumes that the lMP and other on-chip peripherals have been initialized as required by the system hard- ware (timers, chip selects, etc.). E-28 MC68360 USER’S MANUAL MOTOROLA...
Page 451: Initialization
Tx buffer descriptor (after the user sets the R bit) for the next transmission. 22. Write SCM, setting the ENR and ENT bits to enable reception and transmission on the SCC. 23. Prepare more transmit buffers as required to transmit data on the SCC. MOTOROLA MC68360 USER’S MANUAL E-29...
Page 452: Scc Interrupt Handling
Table E-3(b) depicts the general and protocol-specific parameter RAM for each SCC. The SCC registers are shown in Table E-3(c), and the communications processor registers are shown in Table E-3(d). Note that reserved bits in registers should be written as zeros. E-30 MC68360 USER’S MANUAL MOTOROLA...
Page 453 Rx BD 7 Data Pointer (Low Word) Tx BD 7 Data Pointer (Low Word) NOTE: The offset is from the MC68302 base address + ($400 for SCC1, $500 for SCC2, or $600 for SCC3) Table E-1 (b). Transparent Programming Model (Continued)
Page 454: Communications Processor (Cp) Registers
Mask Register (SCCM) Reserved Status Register (SCCS) Reserved Reserved NOTE: The offset is from the MC68302 base address + ($880 for SCC1, $890 for SCC2, or $8A0 for SCC3). Table E-1 (d). General Registers (Only One Set) Initialized Offset Name...
Page 455: Command Register (Cr
0 = One pulse wide prior to the 8-bit data. 1 = N pulses wide and envelopes the N-bit data. SDIAG1, SDIAG0—Serial Interface Diagnostic Mode 00 = Normal operation. 01 = Automatic Echo. 10 = Internal loopback. 11 = Loopback Control. MOTOROLA MC68360 USER’S MANUAL E-33...
Page 456: Serial Interface Mask Register (Simask
$8B2. The SIMASK register is used to configure which bits on the B1 and B2 channels are used in the GCI and IDL modes. Bit 0 of SIMASK is the first bit transmitted and received on B1. E-34 MC68360 USER’S MANUAL MOTOROLA...
Page 457: E.3.1.2 Per Scc Registers
$894 (SCC2), and $8A4 (SCC3) The SCM register configures the operation of the SCC and defines transparent-specific parameters. Note that reserved bits in registers should be writ- ten as zeros. — EXSYN NTSYN REVD — — — — — — DIAG1 DIAG0 MODE1 M0DE0 MOTOROLA MC68360 USER’S MANUAL E-35...
Page 458: Transparent Event Register (Scce
(SCC1), $898 (SCC2), and $8A8 (SCC3) on D15-D8 of a 16-bit data bus. The SCCE is used to report events recognized by the transparent channel. Bits must be cleared by the user to avoid missing interrupt events. Bits are cleared by writing ones to the corresponding bit posi- tions E-36 MC68360 USER’S MANUAL MOTOROLA...
Page 459: Transparent Mask Register (Sccm
SCCE. A bit should be set to a one to enable the corresponding interrupt in the SCCE. Note that reserved bits in registers should be writ- ten as zeros. — IBSY MOTOROLA MC68360 USER’S MANUAL E-37...
Page 460: Transparent Status Register (Sccs
E.3.1.4.1 Receive BD Control/Status Word. To initialize the buffer, the user should write bits15-12 and clear bits1-0. The IMP clears bit 15 when the buffer is closed and sets bits 5- 0 depending on which error occurred. E-38 MC68360 USER’S MANUAL MOTOROLA...
Page 461: Receive Buffer Data Length
E.3.1.5.1 Transmit BD Control/Status Word. To initialize the buffer, the user should write bits 15-11 and clear bits 1-0. The IMP clears bit 15 when the buffer is transmitted or closed due to an error and sets bits 1-0 depending on which error occurred. MOTOROLA MC68360 USER’S MANUAL E-39...
Page 462: Transmit Buffer Pointer
SCC and prepare the SCC for transmission and reception. The algorithm is not specific and assumes that the IMP and other on-chip peripherals have been initialized as required by the system hardware (timers, chip selects, etc.). E.3.2.1 CP INITIALIZATION. E-40 MC68360 USER’S MANUAL MOTOROLA...
Page 463: Scc Initialization
2. Clear any unmasked bits that will be used in this interrupt routine. 3. Handle the interrupt events as required by the system. 4. Clear the appropriate SCC bit in the in-service register (ISR) of the interrupt controller. 5. Return from the interrupt. MOTOROLA MC68360 USER’S MANUAL E-41...
Page 464 SCC Programming Reference E-42 MC68360 USER’S MANUAL MOTOROLA...
Page 465: Appendix Fdesign Checklist
APPENDIX F DESIGN CHECKLIST When integrating the MC68302 into an application, it may be helpful to go through the fol- lowing design checklist. In this checklist are a number of common problems and their reso- lutions that have been found while debugging real MC68302 applications.
Page 466 (see spec 32), or the total system reset may not be terminated correctly and un- usual behavior may occur. Also, when using the RESET instruction to reset the MC68302 internal peripherals, a strong pullup (such as 1.2K ohms) may be required for proper rise times.
Page 467 RAM and do not have predefined values upon a total system reset. 18. Function Code, External Bus Master When an external bus master is using the chip selects on the MC68302 with the ex- ternal master's external memory accesses, make sure that the external bus master drives the function code lines to something other than “111".
Page 468 (e.g., “MOVE #$01, SCCE” clears bit 0 of the SCCE register). 27. Microcode, RAM If microcode from RAM is used (i.e., one of the packages available from Motorola), the microcode must be downloaded into the MC68302 dual-port RAM prior to setting lo- cation $0F8 to $0001.
Page 469 Clear-To-Send Lost 4-92 Control Characters 4-89, 4-102 Arbiter 3-58 CRC Error 4-93 Arbitration 3-14, 3-56, 5-11 DLE 4-85 Bandwidth 3-5, 3-66 DLE-DLE 4-87 Cycle 3-12 DLE-SYNC 4-87 Cycles 3-2, 3-59 DSR 4-88 Error 2-9, 2-11, 2-13 MOTOROLA MC68302 USER’S MANUAL INDEX-1...
Page 470 CD 4-28, 4-40 Command Register 4-5 CEPT 4-19 Communications Processor 4-1 Chip-Select 2-13 Configuration Address Decode Conflict 3-44 MC68302 IMP Control 2-12 AS 3-42 System Registers 2-14 Base Address 3-48 CP 1-6, 4-1 Base Register 3-45 CQFP 7-2 BERR 3-44, 3-46...
Page 471 RMC 3-55 Stack Frame 2-10 SAM 3-55 Vectors 2-8 Vector Generation Enable (VGE) 3-55 EXRQ 3-17 Disabled 4-39, 4-43 EXTAL 3-62, 5-2, 5-4 Disabling the SCCs 4-42 External DISCPU 3-54, 5-6 Bus Master 2-7, 3-58 MOTOROLA MC68302 USER’S MANUAL INDEX-3...
Page 472 AS 3-59 SDS1 4-12 BERR 3-59, 3-60 Signals 4-12 HDLC SIMASK 4-22 Abort Sequence 4-74 SIMODE 4-19 Carrier Detect Lost 4-74 SMC Channels 4-10 Clear-To-Send Lost 4-73 IDL Interface 4-11 CRC 4-69 IDL See Signals INDEX-4 MC68302 USER’S MANUAL MOTOROLA...
Page 473 CPU, See Interrupt, See Signals Acknowledge 2-7, 2-8, 2-11, 2-13, 3-17, 3- IPEND 3-58, See Signals IPL2-IPL0 3-17, 3-19, 5-11, See Interrupt, 19, 3-20 Autovector 2-8, 2-11 See Signals AVEC 3-18, 3-22, 5-12 IPR 4-39 MOTOROLA MC68302 USER’S MANUAL INDEX-5...
Page 474 PCM Highway Mode 4-16 NC1 5-23 RTS 4-18 NC1 See Signals SIMODE 4-19 Nested Interrupt 3-19 Time Slots 4-18 NMSI 4-7, 4-19, 5-14 Pending Interrupt 5-10 BRG1 5-18 Performance 4-23 CD1 5-17 Pin Assignments 7-1 CTS1 5-17 INDEX-6 MC68302 USER’S MANUAL MOTOROLA...
Page 475 RESET 2-19, 3-41, 3-44, 3-62, 5-6, 5-22 Receive BDs 4-34 Instruction 2-7, 2-13, 2-19 Reset 4-39 Reset 4-39 RTS 4-28 SMC Interrupt Requests 4-145 SCC Initialization 4-38 SMC Loopback 4-141 SCCE 4-39 SMC Memory Structure 4-142 SCCM 4-39 MOTOROLA MC68302 USER’S MANUAL INDEX-7...
Page 476 SDMA Retry 4-41 IRQ1 3-17, 5-12 SDS1 4-12, 4-14 IRQ6 3-17 Serial Channels Physical Interface 4-7 IRQ7 3-17, 3-19 Serial Communication Controllers 4-22 L1SY0 4-17, 4-129 Serial Communication Port 4-136, 6-29 NC1 5-23 SIB 3-1 NMSI2 5-18 INDEX-8 MC68302 USER’S MANUAL MOTOROLA...
Page 477 SR (Status Register) 2-2, 2-8, 2-11, 3-17, 3-20 EXSYN 4-129, 4-131 STOP TRANSMIT Command 4-6, 4-36, 4-37, EXSYN Bit 4-129 4-42, 4-88, 4-106 External Sync Mode 4-131 Supervisor FIFO 4-130 Data Space 2-12 GCI 4-130 Stack 2-9 IDL 4-130 MOTOROLA MC68302 USER’S MANUAL INDEX-9...
Page 478 Fractional Stop Bits 4-46, 4-55 Number 2-8, 2-11, 3-22 Frame Format 4-44 Table 2-12 Framing Error 4-55 Vector Generation Enable 3-55 FRZ 4-57 VMA 2-1, See Signals Idle Characters 4-47 VPA 2-11, 5-12, See Signals IDLE Sequence 4-55 INDEX-10 MC68302 USER’S MANUAL MOTOROLA...
Page 479 Index Wait-State 1-5 Wakeup Timer 4-54 Watchdog (WDOG) 3-31, 3-41, 5-22, See Signals, See Timers Hardware 3-59 Timer 3-41 Wired-OR 4-25 Write Protect Violation 3-44, 3-52 XTAL 3-49, 5-4, See Clock, See Signals MOTOROLA MC68302 USER’S MANUAL INDEX-11...
Page 480 Index INDEX-12 MC68302 USER’S MANUAL MOTOROLA...

Motorola MC68302 User Manual

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Number Number

General Description

MC68000/MC68008 Core

System Integration Block (SIB)

Communications Processor (CP)

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