Table of Contents
Advertisement
NOTE
These percentages are valid only when using internal limited request
generation (REQG = 00).
RST - Software Reset
This bit will reset the IDMA to the same state as an external reset. The
IDMA clears RST when the reset is complete.
0 =Normal operation
1 =The channel aborts any external pending or running bus cycles and
terminates channel operation. Setting RST clears all bits in the CSR
and CMR.
STR - Start Operation
This bit starts the IDMA transfer if the REQG bits are programmed for an
internal request. If the REQG bits are programmed for an external request,
this bit must be set before the IDMA will recognize the first request on the
OREO input.
0 =Stop channel; clearing this bit will cause the IDMA to stop transferring
data at the end of the current operand transfer. The IDMA internal
state is not altered.
1 =Start channel; setting this bit will allow the IDMA to start (or continue
if previously stopped) transferring data.
NOTE
STR is cleared automatically when the transfer is complete.
3.1.2.2 SOURCE ADDRESS POINTER REGISTER (SAPR). The SAPR is a 32-bit reg-
ister.
RESERVED
SOURCE ADDRESS POINTER
The SAPR contains 24 (A23-AO) address bits of the source operand used by
the IDMA to access memory or memory-mapped peripheral controller reg-
isters. During the IDMA read cycle, the address on the master address bus
is driven from this register. The SAPR may be programmed by the SAPI bit
to be incremented or remain constant after each operand transfer.
The register is incremented using unsigned arithmetic and will roll over if
an overflow occurs. For example, if a register contains $00FFFFFF and is
incremented by one, it will roll over to $00000000. This register can be in-
cremented by one or two, depending on the SSIZE bit and the starting address
in this register.
MOTOROLA
MC68302 USER'S MANUAL
3-7
Advertisement
Table of Contents
