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Programming Model
Table 11-8. I_EVENT Field Descriptions (Continued)
Bits
Name
25
RXF
Receive frame interrupt. A frame has been received and the last corresponding buffer
descriptor has been updated.
24
RXB
Receive buffer interrupt. A receive buffer descriptor has been updated.
23
MII
MII interrupt. The MII has completed the data transfer requested.
22
EBERR
FEC bus error. A bus error occurred when the FEC was accessing an internal bus.
21
UMINT
Unmasked interrupt status. An interrupt is currently being asserted to the interrupt controller.
This bit is not maskable.
20–0
—
Reserved, should be cleared.
11.5.3 Interrupt Mask Register (I_MASK)
The I_MASK register provides control over which possible interrupt events are allowed to
actually cause an interrupt.This register is cleared upon a hardware reset.
31
30
Field HBERR BABR BABT GRA
Reset
R/W
15
Field
Reset
R/W
Addr
Table 11-9. I_MASK Register Field Descriptions
Bits
Name
31–22
See
Figure 11-6
21–0
—
11.5.4 Interrupt Vector Status Register (IVEC)
The IVEC register gives status indicating the class of interrupt being generated by the FEC.
Interrupt level control is provided in the interrupt control registers of the SIMBC.
11-14
29
28
27
26
TXF
TXB
0000_0000_0000_0000
0000_0000_0000_0000
Figure 11-6. I_MASK Register
Interrupt mask. Each bit corresponds to an interrupt source defined by the I_EVENT
register. The corresponding I_MASK bit determines whether an interrupt condition can
generate an interrupt. At every clock, the I_EVENT samples the signal generated by the
interrupting source. The corresponding I_EVENT bit reflects the state of the interrupt
signal even if the corresponding I_MASK bit is set.
0 The corresponding interrupt source is not masked .
1 The corresponding interrupt source is masked.
Reserved, should be cleared.
MCF5272 User's Manual
Description
25
24
23
RXF
RXB
MII
EBERR
Read/write
—
Read/write
MBAR + 0x848
Description
22
21
—
16
0
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