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PIN CONFIGURATION
THC63LVDM83R
1
RS
2
TD1
3
TA5
4
TA6
5
GND
6
TB0
7
TB1
8
TD2
9
VCC
10
TD3
11
TB2
12
TB3
13
GND
14
TB4
15
TB5
16
TD4
17
R/F
18
TD5
19
TB6
20
TC0
21
GND
22
TC1
23
TC2
24
TC3
25
TD6
26
VCC
27
TC4
28
TC5
THC63LVDM83R
BLOCK DIAGRAM
56
TA4
55
TA3
54
TA2
53
GND
52
TA1
51
TA0
50
TD0
49
LVDS GND
48
TA-
47
TA+
46
TB-
45
TB+
44
LVDS VCC
43
LVDS GND
42
TC-
41
TC+
40
TCLK -
39
TRANSMITTER
TCLK+
38
CLOCK IN
TD-
37
(20 to 85MHz)
TD+
36
LVDS GND
35
PLL GND
34
PLL VCC
33
PLL GND
32
/PDWN
31
CLK IN
30
TC6
29
GND
THC63LVDM83R
7
TA0-6
7
TB0-6
7
TC0-6
7
TD0-6
PLL
R/F
/PDWN
RS
DATA
(LVDS)
TA +/-
TB +/-
TC +/-
TD +/-
(140-595Mbit/On Each
LVDS Channel)
TCLK +/-
CLOCK
(LVDS)
20~85MHz
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