Motorola MVME172-233 Manuals

Manuals and User Guides for Motorola MVME172-233. We have 1 Motorola MVME172-233 manual available for free PDF download: Programmer's Reference Manual

Motorola MVME172-233 Programmer's Reference Manual

Motorola MVME172-233 Programmer's Reference Manual (354 pages)

VME Embedded Controller

Brand: Motorola | Category: Controller | Size: 3.34 MB

Table of Contents

Table of Contents
7
CHAPTER 1 Board Description and Memory Maps

19
CHAPTER 2 Vmechip2

79
CHAPTER 3 MC2 Chip

189
- Introduction
  189
  - Summary of Major Features
    189
- Functional Description
  190
  - MC2 Chip Initialization
    190
  - Flash and PROM Interface
    190
  - BBRAM Interface
    191
  - 82596CA LAN Interface
    191
    
    MPU Port and MPU Channel Attention
    191
    
    MC68060-Bus Master Support for 82596CA
    192
    
    LANC Bus Error
    192
    
    LANC Interrupt
    193
  - 53C710 SCSI Controller Interface
    193
  - SRAM Memory Controller
    193
  - NON-ECC DRAM Memory Controller
    193
  - Z85230 SCC Interface
    194
  - Table 3-1. DRAM Performance
    194
  - Tick Timers
    195
  - Watchdog Timer
    196
  - Local Bus Timer
    196
- Memory Map of the MC2 Chip Registers
  196
- Table 3-2. MC2 Chip Register Map
  197
- Programming Model
  198
  - MC2 Chip ID Register
    199
  - MC2 Chip Revision Register
    199
  - General Control Register
    200
  - Interrupt Vector Base Register
    201
  - Table 3-3. Interrupt Vector Base Register Encoding and Priority
    202
  - Programming the Tick Timers
    203
    
    Tick Timer 1 and 2 Compare and Counter Registers
    203
    
    LSB Prescaler Count Register
    205
    
    Prescaler Clock Adjust Register
    206
    
    Tick Timer 1 and 2 Control Registers
    206
    
    Tick Timer Interrupt Control Registers
    208
  - DRAM Parity Error Interrupt Control Register
    210
  - SCC Interrupt Control Register
    211
  - Tick Timer 3 and 4 Control Registers
    212
  - DRAM and SRAM Memory Controller Registers
    213
    
    DRAM Space Base Address Register
    213
    
    SRAM Space Base Address Register
    214
    
    DRAM Space Size Register
    214
    
    DRAM/SRAM Options Register
    215
    
    Table 3-4. DRAM Size Control Bit Encoding
    215
    
    Table 3-5. DRAM Size Control Bit Encoding
    216
    
    Table 3-6. SRAM Size Control Bit Encoding
    216
    
    SRAM Space Size Register
    217
    
    Table 3-7. SRAM Size Control Bit Encoding
    217
  - LANC Error Status Register
    218
  - 82596CA LANC Interrupt Control Register
    219
  - LANC Bus Error Interrupt Control Register
    220
  - SCSI Error Status Register
    221
  - General Purpose Inputs Register
    221
  - MVME172 Version Register
    223
  - SCSI Interrupt Control Register
    224
  - Tick Timer 3 and 4 Compare and Counter Registers
    225
  - Bus Clock Register
    226
  - PROM Access Time Control Register
    227
  - Flash Access Time Control Register
    228
  - ABORT Switch Interrupt Control Register
    229
  - RESET Switch Control Register
    230
  - Watchdog Timer Control Register
    231
  - Access and Watchdog Time Base Select Register
    232
  - DRAM Control Register
    233
  - MPU Status Register
    234
  - 32-Bit Prescaler Count Register
    236
CHAPTER 4 IP2 Chip

237
- Introduction
  237
  - Summary of Major Features
    237
- Functional Description
  238
  - General Description
    238
  - Cache Coherency
    238
  - Local Bus to Industrypack DMA Controllers
    239
  - Clocking Environments and Performance
    241
  - Table 4-1. IP2 Chip Clock Cycles
    242
  - Programmable Clock
    243
  - Error Reporting
    243
    
    Error Reporting as a Local Bus Slave
    243
    
    Error Reporting as a Local Bus Master
    243
    
    Industrypack Error Reporting
    244
  - Interrupts
    244
- Overall Memory Map
  245
- Table 4-2. IP2 Chip Overall Memory Map
  245
- Programming Model
  246
- Local Bus to Industrypack Addressing
  282
  - 8-Bit Memory Space
    282
  - 16-Bit Memory Space
    283
  - 32-Bit Memory Space
    284
  - Ip_A I/O Space
    285
  - Ip_Ab I/O Space
    286
  - Ip_A ID Space
    287
- IP to Local Bus Data Routing
  288
  - Memory Space Accesses
    288
  - I/O and ID Space Accesses
    290
Chapter 5 Mcecc

291
- Introduction
  291
- Features
  291
- Functional Description
  292
  - Performance
    292
  - General Description
    292
  - Table 5-1. MCECC Specifications
    293
  - Cache Coherency
    293
  - Ecc
    294
    
    Cycle Types
    294
    
    Error Reporting
    295
    
    Single Bit Error (Cycle Type = Burst Read or Non-Burst Read)
    295
    
    Double Bit Error (Cycle Type = Burst Read or Non-Burst Read)
    295
    
    Triple (or Greater) Bit Error (Cycle Type = Burst Read or Non-Burst Read)
    296
    
    Cycle Type = Burst Write
    296
    
    Single Bit Error (Cycle Type = Non-Burst Write)
    296
    
    Double Bit Error (Cycle Type = Non-Burst Write)
    296
    
    Triple (or Greater) Bit Error (Cycle Type = Non-Burst Write)
    296
    
    Single Bit Error (Cycle Type = Scrub)
    296
    
    Double Bit Error (Cycle Type = Scrub)
    297
    
    Triple (or Greater) Bit Error (Cycle Type = Scrub)
    297
  - Error Logging
    297
  - Scrub
    297
  - Refresh
    298
  - Arbitration
    298
  - Chip Defaults
    298
- Programming Model
  299
  - Table 5-2. MCECC Internal Register Memory Map, Part 1
    300
  - Chip ID Register
    304
  - Chip Revision Register
    304
  - Memory Configuration Register
    305
  - Dummy Register 0
    306
  - Base Address Register
    307
  - Dummy Register 1
    307
  - DRAM Control Register
    308
  - BCLK Frequency Register
    310
  - Data Control Register
    311
    
    Scrub Control Register
    313
    
    Scrub Period Register Bits 15-8
    314
    
    Scrub Period Register Bits 7-0
    314
    
    Chip Prescaler Counter
    315
    
    Scrub Time On/Time off Register
    315
    
    Scrub Prescaler Counter (Bits 21-16)
    317
    
    Scrub Prescaler Counter (Bits 15-8)
    318
    
    Scrub Prescaler Counter (Bits 7-0)
    318
    
    Scrub Timer Counter (Bits 15-8)
    318
    
    Scrub Timer Counter (Bits 7-0)
    319
    
    Scrub Address Counter (Bits 26-24)
    319
    
    Scrub Address Counter (Bits 23-16)
    320
    
    Scrub Address Counter (Bits 15-8)
    320
    
    Scrub Address Counter (Bits 7-4)
    321
    
    Error Logger Register
    321
    
    Error Address (Bits 31-24)
    322
    
    Error Address (Bits 23-16)
    323
    
    Error Syndrome Register
    324
    
    Defaults Register 2
    324
    
    Defaults Register 2
    326
    
    Initialization
    327
  - Syndrome Decode
    329
- Table A-1. Motorola Computer Group Documents
  333
APPENDIX A Related Documentation

334
- Literature Updates
  334
- Manufacturers' Documents
  334
- Table A-2. Manufacturers' Documents
  334
APPENDIX B Using Interrupts on the MVME172

337
- Introduction
  337
- Vmechip2 Tick Timer 1 Periodic Interrupt Example
  337
Index

341

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