Motorola MC68EC060 Manuals

Manuals and User Guides for Motorola MC68EC060. We have 1 Motorola MC68EC060 manual available for free PDF download: User Manual

Motorola MC68EC060 User Manual

Motorola MC68EC060 User Manual (416 pages)

Brand: Motorola | Category: Computer Hardware | Size: 1.42 MB

Table of Contents

Table of Contents

7
List of Illustrations

17
- Introduction
  
  27
  - 1.1 Differences Among M68060 Family Members
    27
  - 1.1.1 Mc68Lc060
    27
  - 1.1.2 Mc68Ec060
    27
  - Address Translation Differences
    27
  - Instruction Differences
    27
  - 1.2 Features
    28
  - 1.3 Architecture
    28
  - 1.4 Processor Overview
    29
  - 1.4.1 Functional Blocks
    29
  - Integer Unit
    30
  - Instruction Fetch Unit
    30
    
    MC68060 Block Diagram
    30
  - 1.4.2 Integer Unit
    31
  - Floating-Point Unit
    32
  - Memory Units
    33
  - Address Translation Caches
    33
  - Instruction and Data Caches
    33
  - Cache Organization
    34
  - Cache Coherency
    34
  - 1.4.3 Bus Controller
    34
  - 1.5 Processing States
    34
  - 1.6 Programming Model
    35
  - Programming Model
    36
  - Data Format Summary
    38
  - 1.8 Addressing Capabilities Summary
    38
    
    Data Formats
    38
  - 1.9 Instruction Set Overview
    39
    
    Effective Addressing Modes
    39
  - Instruction Set Summary
    40
  - 1.10 Notational Conventions
    45
- Signal Description
  
  47
  - Signal Index
    47
  - 2.1 Address and Control Signals
    49
  - Address Bus (A31-A0)
    49
    
    Functional Signal Groups
    49
  - Cycle Long-Word Address (CLA)
    50
  - Data Bus (D31-D0)
    50
  - 2.3 Transfer Attribute Signals
    50
  - Transfer Cycle Type (TT1, TT0)
    50
  - Transfer Cycle Modifier (TM2-TM0)
    50
    
    Transfer-Type Encoding
    50
  - Transfer Line Number (TLN1, TLN0)
    52
  - User-Programmable Page Attributes (UPA1, UPA0)
    52
    
    Normal and MOVE16 Access Tmx Encoding
    52
    
    Alternate Access Tmx Encoding
    52
  - Read/Write (R/W)
    53
    
    Sizx Encoding
    53
  - Data Bus Byte Select Signals
    54
  - 2.14 Signal Summary
    63
  - MC68060 Integer Unit Pipeline
    65
  - Integer Unit User Programming Model
    66
  - Integer Unit Supervisor Programming Model
    67
  - Processor Configuration Register
    69
  - Memory Management Unit
    71
  - Memory Management Programming Model
    72
  - URP and SRP Register Formats
    72
  - Translation Control Register Format
    73
  - Transparent Translation Register Format
    75
  - Translation Table Structure
    77
  - Logical Address Format
    77
  - Detailed Flowchart of Table Search Operation
    79
  - Detailed Flowchart of Descriptor Fetch Operation
    80
  - Page Descriptor Formats
    81
  - Example Translation Table
    84
  - Translation Table Using Indirect Descriptors
    85
  - Updating U-Bit and M-Bit for
    89
  - SFC and DFC Values
    89
  - Translation Table Structure for Two Tasks
    90
  - Logical Address Map with Shared Supervisor and User Address Spaces
    91
  - Translation Table Using S-Bit and W-Bit to Set Protection
    92
  - ATC Organization
    93
  - ATC Entry and Tag Fields
    94
  - Address Translation Flowchart
    98
  - MC68060 Instruction and Data Caches
    101
  - Instruction Cache Line Format
    101
  - Data Cache Line Format
    101
  - Caching Operation
    102
  - Tlnx Encoding
    110
  - Instruction Cache Line State Diagram
    116
  - Instruction Cache Line State Transitions
    116
  - Data Cache Line State Diagrams
    117
  - Data Cache Line State Transitions
    118
  - Floating-Point Unit Block Diagram
    120
  - Floating-Point User Programming Model
    121
  - Floating-Point Control Register Format
    122
  - RND Encoding
    122
  - PREC Encoding
    122
  - Floating-Point Condition Code (FPSR)
    123
  - Floating-Point Quotient Byte (FPSR)
    123
  - Floating-Point Exception Status Byte (FPSR)
    124
  - Floating-Point Accrued Exception Byte (FPSR)
    124
  - MC68060 FPU Data Formats and Data Types
    125
  - Single-Precision Real Format Summary
    126
  - Double-Precision Real Format Summary
    127
  - Extended-Precision Real Format Summary
    128
  - Packed Decimal Real Format Summary
    129
  - Intermediate Result Format
    130
  - Rounding Algorithm Flowchart
    132
  - Floating-Point Condition Code Encoding
    134
  - Floating-Point Conditional Tests
    136
  - Floating-Point Exception Vectors
    137
  - Unimplemented Instructions
    138
  - Possible Operand Errors Exceptions
    145
  - Overflow Rounding Mode Values
    147
  - Underflow Rounding Mode Values
    149
  - Possible Divide-By-Zero Exceptions
    151
  - Rounding Mode Values
    152
  - Floating-Point State Frame
    153
  - Status Word Contents
    154
  - Signal Relationships to Clocks
    157
  - Full-Speed Clock
    157
  - Half-Speed Clock
    157
  - Quarter-Speed Clock
    158
  - Bus Control Register Format
    159
  - Internal Operand Representation
    160
  - Data Multiplexing
    161
  - Data Bus Requirements for Read and Write Cycles
    162
  - Byte Select Signal Generation and PAL Equation
    163
  - Summary of Access Types Vs. Bus Signal Encoding
    164
  - Example of a Misaligned Long-Word Transfer
    165
  - Example of Misaligned Word Transfer
    165
  - Misaligned Long-Word Read Bus Cycle Timing
    166
  - Memory Alignment Influence on Noncachable and Writethrough Bus Cycles
    167
  - Byte, Word, and Long-Word Read Cycle Flowchart
    168
  - Byte, Word, and Long-Word Read Bus Cycle Timing
    169
  - Line Read Cycle Flowchart
    172
  - Line Read Transfer Timing
    173
  - Burst-Inhibited Line Read Cycle Flowchart
    175
  - Burst-Inhibited Line Read Bus Cycle Timing
    176
  - Byte, Word, and Long-Word Write Transfer Flowchart
    177
  - Long-Word Write Bus Cycle Timing
    178
  - Line Write Cycle Flowchart
    181
  - Line Write Burst-Inhibited Cycle Flowchart
    182
  - Line Write Bus Cycle Timing
    183
  - Locked Bus Cycle for TAS Instruction Timing
    185
  - Using CLA in a High-Speed DRAM Design
    188
  - Interrupt Pending Procedure
    188
  - Assertion of IPEND
    189
  - Interrupt Acknowledge Termination Summary
    189
  - Interrupt Acknowledge Cycle Flowchart
    191
  - Interrupt Acknowledge Bus Cycle Timing
    192
  - Autovector Interrupt Acknowledge Bus Cycle Timing
    193
  - Breakpoint Interrupt Acknowledge Cycle Flowchart
    194
  - Breakpoint Interrupt Acknowledge Bus Cycle Timing
    195
  - LPSTOP Broadcast Cycle Flowchart
    196
  - LPSTOP Broadcast Bus Cycle Timing, BG Negated
    197
  - LPSTOP Broadcast Bus Cycle Timing, BG Asserted
    198
  - Exiting LPSTOP Mode Flowchart
    199
  - Exiting LPSTOP Mode Timing Diagram
    200
  - Termination Result Summary
    201
  - Word Write Access Bus Cycle Terminated with TEA Timing
    203
  - Line Read Access Bus Cycle Terminated with TEA Timing
    204
  - Retry Read Bus Cycle Timing
    205
  - Line Write Retry Bus Cycle Timing
    206
  - MC68040-Arbitration Protocol Transition Conditions
    210
  - MC68040-Arbitration Protocol State Description
    211
  - MC68040-Arbitration Protocol State Diagram
    212
  - MC68060-Arbitration Protocol State Transition Conditions
    217
  - MC68060-Arbitration Protocol State Description
    218
  - MC68060-Arbitration Protocol State Diagram
    219
  - Processor Bus Request Timing
    222
  - Arbitration During Relinquish and Retry Timing
    223
  - Implicit Bus Ownership Arbitration Timing
    224
  - Effect of BGR on Locked Sequences
    225
  - Snooped Bus Cycle
    226
  - Initial Power-On Reset Timing
    227
  - Normal Reset Timing
    228
  - Data Bus Usage During Reset
    229
  - Special Mode Vs. Iplx Signals
    229
  - Acknowledge Termination Ignore State Example
    230
  - Extra Data Write Hold Example
    232
  - General Exception Processing Flowchart
    234
  - General Form of Exception Stack Frame
    235
  - Exception Vector Assignments
    236
  - Interrupt Levels and Mask Values
    244
  - Interrupt Recognition Examples
    245
  - Interrupt Exception Processing Flowchart
    247
  - Reset Exception Processing Flowchart
    248
  - Exception Priority Groups
    249
  - Fault Status Long-Word Format
    254
  - JTAG States
    263
  - JTAG Test Logic Block Diagram
    264
  - JTAG Instructions
    264
  - JTAG Idcode Register Format
    268
  - Output Pin Cell (O.pin)
    269
  - Observe-Only Input Pin Cell (I.obs)
    269
  - Input Pin Cell (I.pin)
    270
  - Output Control Cell (Io.ctl)
    270
  - General Arrangement of Bidirectional Pin Cells
    271
  - Boundary Scan Bit Definitions
    271
  - JTAG Bypass Register
    276
  - Circuit Disabling IEEE Standard 1149.1
    277
  - Debug Command Interface Schematic
    286
  - Debug Command Interface Pins
    286
  - Interface Timing
    287
  - Command Summary
    289
  - Transition from JTAG to Debug Mode Timing Diagram
    295
  - Transition from Debug to JTAG Mode Timing Diagram
    296
  - Superscalar OEP Dispatch Test Algorithm
    300
  - MC68060 Superscalar Classification of M680X0 Integer Instructions
    300
  - Superscalar Classification of M680X0 Privileged Instructions
    303
  - Superscalar Classification of M680X0 Floating-Point Instructions
    303
  - 10.4 Effective Address Calculation Times
    310
  - Move Byte and Word Execution Times
    311
  - Move Long Execution Times
    311
  - MOVE16 Execution Times
    311
  - Standard Instruction Execution Time
    312
  - 10.7 Immediate Instruction Execution Times
    313
  - 10.8 Single-Operand Instruction Execution Times
    314
  - Clear (CLR) Execution Times
    314
  - 10.9 Shift/Rotate Execution Times
    315
  - Bit Manipulation (Dynamic Bit Count) Execution Times
    315
  - Bit Manipulation (Static Bit Count) Execution Times
    316
  - Bit Field Execution Times
    316
  - Branch Execution Times
    317
  - JMP, JSR Execution Times
    317
  - Return Instruction Execution Times
    317
  - Status Register
    318
  - LEA, PEA, and MOVEM Instruction Execution Times
    318
  - 10.13 Multiprecision Instruction Execution Times
    318
  - Status Register (SR) Instruction Execution Times
    319
  - MOVES Execution Times
    319
  - Miscellaneous Instruction Execution Times
    319
  - Floating-Point Instruction Execution Times
    320
  - 10.16 Exception Processing Times
    322
  - Cache Control Register
    325
  - Linear Voltage Regulator Solution
    329
  - LTC1147 Voltage Regulator Solution
    330
  - LTC1148 Voltage Regulator Solution
    331
  - MAX767 Voltage Regulator Solution
    332
  - MC68040 Address Hold Time
    333
  - MC68060 Address Hold Time
    334
  - MC68060 Address Hold Time Fix
    334
  - Simple CLK Generation
    336
  - Generic CLK Generation
    336
  - 11.2.7 Pstx Encoding
    336
  - MC68040 BCLK to CLKEN Relationship
    337
  - DRAM Timing Analysis
    337
  - With Heat Sink, no Air Flow
    340
  - With Heat Sink, with Air Flow
    340
  - No Heat Sink
    341
  - Support Devices and Products
    342
  - Clock Input Timing Diagram
    345
  - Reset Configuration Timing
    348
  - Read/Write Timing
    349
  - Bus Arbitration Timing
    350
  - Bus Arbitration Timing (Continued)
    351
  - CLA Timing
    352
  - Snoop Timing
    353
  - Other Signals Timing
    354
  - PGA Package Dimensions (RC Suffix)
    358
  - QFP Package Dimensions (FE Suffix)
    359
  - Call-Out Dispatch Table Example
    363
  - Example Pseudo-Assembly File
    364
  - Module Call-In, Call-Out Example
    365
  - Call-Out Dispatch Table and Module Size
    365
  - CAS and CAS2 Call-Outs and Entry Points
    370
  - C-Code Representation of Integer Library Routines
    371
  - MUL Instruction Call Example
    372
  - CMP2 Instruction Call Example
    372
  - FPU Comparison
    373
  - Unimplemented Instructions
    374
  - Unimplemented Data Formats and Data Types
    374
  - SNAN/OPERR Exception Handler Pseudo-Code
    379
  - Disabled Vs. Enabled Exception Actions
    381
  - UNIX Operating System Calls
    384
  - Register Usage of {I,D}Mem_{Read,Write}_{B,W,L
    386
  - Instructions Not Handled by the M68060SP
    387
  - Files Provided in an M68060SP Release
    388
  - Vector Table and M68060SP Relationship
    389
  - M68000 Family Instruction Set and Processor Cross-Reference
    391
  - M68000 Family Instruction Set
    396
  - Exception Vector Assignments for the M68000 Family
    400

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