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Samsung KS8910 User Manual
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Samsung KS8910 User Manual

Samsung KS8910 User Manual

100/10 mbps ethernet transceriver
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20-8910-0599
USER'S MANUAL
KS8910
100/10 Mbps Ethernet Transceriver(PHY)
Preliminary

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  • Page 1 20-8910-0599 USER'S MANUAL KS8910 100/10 Mbps Ethernet Transceriver(PHY) Preliminary...

  • Page 2: Important Notice

    All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics.
  • Page 3 The KS8910 100/10 Mbps Ethernet Transceiver User’ s Manual is intended for application designers and programmers who are using the KS8910 100/10 Mbps ethernet microcontroller for product development. The first six sections of this manual give you a general orientation to the KS8910 100/10 Mbps ethernet transceriver: •...
  • Page 4 PRELIMINARY SPECIFICATION KS8910 100/10 Mbps ETHERNET CONTROLLER...

  • Page 5: Table Of Contents

    Carrier Sense ..........................4-9 Physical Medium Attachment (PMA) ...................... 4-10 Scrambling ............................. 4-10 Link Monitor ............................ 4-12 NRZ to NRZI AND NRZI to NRZ ConversiON ................4-13 Physical Medium Dependent sublayer ....................4-14 PRELIMINARY SPECIFICATION KS8910 100/10 Mbps ETHERNET CONTROLLER...
  • Page 6 100Base-TX Control Register : Register 17 ...................7-12 PHY Address Register : Register 18 ....................7-12 Map Table Register 0 : Register 19 ....................7-13 Map Table Register 1 : Register 20 ....................7-13 Analog Control Register 0 : Register 21 ..................7-14 PRELIMINARY SPECIFICATION viii KS8910 100/10 Mbps ETHERNET CONTROLLER...
  • Page 7 NIC Applications ............................. 9-1 KS9820 MAC Ethernet Controller Application ................9-1 Section 10 Mechanical Data Package Dimension ..........................10-1 Section 11 Appendix Glossary ..............................11-1 Ethernet and Networking Acronyms and Terms ................11-1 PRELIMINARY SPECIFICATION KS8910 100/10 Mbps ETHERNET CONTROLLER...
  • Page 8 Analog Blocks of KS8910 ....................3-5 100Base-TX Operational Block Diagram of KS8910 ............4-3 PCS Functional Block Diagram of KS8910 ...............4-4 4B/5B Encoder (Transmit) State Diagram of KS8910 ............4-7 5B/4B Decoder (Receive) State Diagram of KS8910 ............4-8 Linear Feedback Shift Register (LFSR) ................4-10 Scrambler Function of KS8910 ..................4-10...
  • Page 9 List of Tables Table Number Title Page Number KS8910 Signal Descriptions ....................2-4 4B/5B Coding of KS8910 ....................4-5 5B/4B Outputs ........................4-6 Transmit Clocks Generated by the Frequency Synthesizer ..........6-4 Address Mapping ......................7-2 Absolute Maximum Ratings (T = 25 °C) ................

  • Page 10: Product Overview

    PRODUCT OVERVIEW INTRODUCTION The KS8910 10Base-T/100Base-TX Ethernet transceiver is fully compliant with the IEEE 802.3u specification, provides configurable 100Mbs support for Category 5 unshielded twisted pair (UTP) and supports 10Mbs operation on Category 3 UTP or Category 5 UTP. The transceiver provides an electrical interface between the Media Independent Interface (MII) of the Media Access Controller (MAC) and the physical wire pair, and includes support for the basic and extended register set of station management registers.

  • Page 11: Features

    Preliminary Spec. ver PRODUCT OVERVIEW KS8910 100/10 Mbps ETHERNET TRANSCEIVER FEATURES • Support for old and new media : Compatible with existing 10-Mbit/s networks. • 10BASE-T/100-BASE-TX operation : Range of price/performance points, Phased Conversion • Full IEEE 802.3 compatibility : Compatible with existing hardware and software.

  • Page 12: Ethernet 10Base-T And 100Base-Tx Block Diagram

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER PRODUCT OVERVIEW 10Base-T 10/100Mbps 10/100Mbps Transformer Processor 100Base-TX KS8910 KS8920 Figure 1-2. Ethernet System Overview Diagram with Emphasis on MDI ETHERNET 10BASE-T AND 100BASE-TX BLOCK DIAGRAM 20MHz 20MHz Registers Auto-Negotiation Station MDIO...

  • Page 13: Reference Documents

    Preliminary Spec. ver PRODUCT OVERVIEW KS8910 100/10 Mbps ETHERNET TRANSCEIVER REFERENCE DOCUMENTS Supplement to ANSI/IEEE Std 802.3, 1993 Edition. Supplement to Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method & Physical Layer Specifications: “MAC Parameters, Physical Layer, Medium Attachment Units and Repeater for 100 Mb/s Operation”...

  • Page 14: External Signals

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER EXTERNAL SIGNALS EXTERNAL SIGNALS OVERVIEW Figure 2-1 shows the 44 external signals for the 10/100 Mbit/s Ethernet Physical Layer Transceiver, divided into functional groups. Power and ground pins need to be added to this signal list. The device will require a 64 pin package.

  • Page 15: External Signals

    Preliminary Spec. ver EXTERNAL SIGNALS KS8910 100/10 Mbps ETHERNET TRANSCEIVER EXTERNAL SIGNALS TPOP Tx_clk TPON Transmit Twisted TxD[3:0] Media TPOB Pair Independent Interface Tx_en TPIP Interface(MII) Tx_er TPIN XTAL_IN Rx_clk Receive XTAL_OUT Analog Pins Media RxD[3:0] Independent Rx_DV Interface(MII) Rx_er...

  • Page 16: Pin Assignments

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER EXTERNAL SIGNALS PIN ASSIGNMENTS Rx_DV TPIP Rx_clk TPIN Rx_er SUBANA Tx_er SP_SEL Tx_clk VDDREF SUBDIG VSSREF KS8910 SUBIO 64QFP-1414 VSSIO RBGND Top View VDDIO AN_EN Tx_en TPON TxD0 VSSDRV TxD1 TPOP TxD2...

  • Page 17: Signal Descriptions

    Preliminary Spec. ver EXTERNAL SIGNALS KS8910 100/10 Mbps ETHERNET TRANSCEIVER SIGNAL DESCRIPTIONS Table 2-1. KS8910 Signal Descriptions Signal Pin Number Description MEDIA INDEPENDENT INTERFACE (MII) SIGNALS The MII is the interface between the 10/100 Mbit/s Ethernet Transceiver and a Media Access Control (MAC) device.
  • Page 18 Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER EXTERNAL SIGNALS Table 2-1. KS8910 Signal Descriptions Signal Pin Number Description Receive clock : Rx_clk Rx_clk is a continuous clock. In 4-bit mode, its frequency is 25 MHz for 100Mbit/s operation, and 2.5 MHz for 10Mbit/s. RXD[3:0], Rx_DV, and Rx_er are driven by the Transceiver off the falling edge of Rx_clk, and sampled on the rising edge of Rx_clk.
  • Page 19 Preliminary Spec. ver EXTERNAL SIGNALS KS8910 100/10 Mbps ETHERNET TRANSCEIVER Table 2-1. KS8910 Signal Descriptions Signal Pin Number Description LEDR[D1] Receive Indicator /Device ID1: LEDS[D0] Speed Indicator /Device ID0: Pulled low when 100Mbit/s operation is in affect either by manual selection or after Arbitration.
  • Page 20 Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER EXTERNAL SIGNALS Table 2-1. KS8910 Signal Descriptions Signal Pin Number Description Power and Ground Signals VDDDIG 2,47 3.3V Power Supply for Digital Internal Block VDDIO 10,39,57 3.3V Power Supply for Digital I/O Block VDDTXA 3.3V Power Supply for Analog Block...
  • Page 21 Preliminary Spec. ver EXTERNAL SIGNALS KS8910 100/10 Mbps ETHERNET TRANSCEIVER MEMO...

  • Page 22: Functional Blocks

    FINCTIONAL BLOCKS FUNCTIONAL BLOCKS This section of the specification provides a description of the functional blocks of the KS8910 10/100 Mbit/s Ethernet Transceiver architecture. The next Chapter of the document will describe the blocks in detail. Shown in Figure 3-1 are the functional blocks in the architecture.

  • Page 23: Management Agent

    The Auto-negotiation function provides the Auto-Negotiation Transmit, Receive, Arbitration, and Normal Link Pulses (NLP) receive link integrity test functions. The Auto-negotiation functions interact with technology dependent PMA’ s through the technology dependent interface. The Technology dependent interface includes 10Base-T/100Base-TX and 100Base-T4.The KS8910 does not support 100Base-T4.

  • Page 24: Base-Tx Digital Block

    5B/4B P ¡ ç S DeScrambler Figure 3-2. 100Base-TX Digital Bolck of KS8910 4B/5B The symbol encoder converts 4-bit (4B) nibble data generated by the MAC into 5-bit (5B) symbols for transmission. This conversion is required to allow control symbols to be combined with data symbols.
  • Page 25 Preliminary Spec. ver FUNCTIONAL BLOCKS KS8910 100/10 Mbps ETHERNET TRANSCEIVER Serial Scrambler The Serial Scrambler is used to minimize electromagnetic emissions from the TP-PMD physical link. Serial Scrambling randomizes the data spectrum by the addition of a pseudo-random key sequence to the plain-text sequence transmitted by the PHY.

  • Page 26: 10Base-T Digital Block

    A carrier event is in error if it does not start with a Start-of-Stream Delimiter. 10Base-T Digital Block Diagram 100BASE-TX AND 10BASE-T ANALOG BLOCKS Figure 3-3 shows the Analog Blocks of KS8910 10/100 Mbit/s Ethernet Transceiver. 10Mbit/s Analog Block TXPLL...
  • Page 27 LED DRIVER The KS8910 supports five status LEDs and LED pins are shared with PHY address.These pins can be externally strapped as ‘ H igh’ or ‘ L ow’ to encode different PHY addresses. When the pin is strapped to Low, the associated...

  • Page 28: 100 Base-Tx Digital Blocks

    This chapter describes the physical coding sublayer (PCS), physical medium attachment (PMA) sublayer, and the physical medium dependent sublayer (PMD) for comprehension of the 100Base-TX within the KS8910. This is based upon the IEEE 802.3U/D5.3 specification and ANSI X3.263:1995 TP-PMD, Revision 2.2 (1 March 1995) specification.

  • Page 29: Physical Medium Attachment Sublayer (Pma)

    PHYSICAL MEDIUM DEPENDENT SUBLAYER (PMD) The KS8910’ s PMD receives NRZI code-bits from the PMA, encodes them into MLT-3, and transmits them to the adjacent PMD over the physical link. The PMD also decodes the incoming bits and delivers them to the PMA in NRZI format.

  • Page 30: Base-Tx Operational Block Diagram Of Ks8910

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER 100BASE-TX DIGITAL BLOCKS Figure 4-1. 100Base-TX Operational Block Diagram of KS8910...

  • Page 31: Physical Coding Sublayer (Pcs)

    100BASE-TX DIGITAL BLOCKS KS8910 100/10 Mbps ETHERNET TRANSCEIVER PHYSICAL CODING SUBLAYER (PCS) The KS8910 PCS maps data and control signals between the MII and PMA. The PCS consists of five functional blocks as it appears in Figure 4-2. RxD[3:0] TxD[3:0]...

  • Page 32: B/5B Coding Of Ks8910

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER 100BASE-TX DIGITAL BLOCKS Table 4-1. 4B/5B Coding of KS8910 4B Code 5B Symbol Code Type Name Interpretation [3:0] [4:0] 0000 11110 “0” Data 0001 01001 “1” Data 0010 10100 “2” Data 0011 10101 “3”...

  • Page 33: 5B Encoder (Transmit Stm)

    Preliminary Spec. ver 100BASE-TX DIGITAL BLOCKS KS8910 100/10 Mbps ETHERNET TRANSCEIVER 4B/5B ENCODER (TRANSMIT STM) The 4B/5B Encoder converts the received data nibbles into 5-bit code groups. This is a trivial translation process except for the first two nibbles of the preamble which are substituted by the Start-of-Stream Delimiter, SSD.

  • Page 34: B/5B Encoder (Transmit) State Diagram Of Ks8910

    TXbits = ‘ e sd1 END STREAM R END STREAM T sent_code * transmitting = 0 sent_code * COL= 0 transmitting = 0 TXbits = ‘ e sd2 COL= 0 TXbits = idle Figure 4-3. 4B/5B Encoder (Transmit) State Diagram of KS8910...

  • Page 35: B/4B Decoder (Receive) State Diagram Of Ks8910

    = 1 RX_DV = 0/1 RX_DV = 0/1 RX_ER = 0/1 RX_ER = 0/1 RXD = decode(RXbits[9:5]) RXD = 4’ h 0 / 4’ h 0 INIT_RBITS = 0/1 INIT_RBITS = 0 Figure 4-4. 5B/4B Decoder (Receive) State Diagram of KS8910...

  • Page 36: Parallel And Serial Converters

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER 100BASE-TX DIGITAL BLOCKS PARALLEL AND SERIAL CONVERTERS Serial Converter (Transmit Bits STM) The Serial Converter receives a stream of 5-bit code-groups in parallel form from the Encoder and converts it into a serial bit stream which is then forwarded to the PMA.

  • Page 37: Physical Medium Attachment (Pma)

    LFSR is given Figure 4-5 whereas a functional block diagram of the scrambler s in Figure 4-6. lfsr_out Tx_clk Tx_en cl/st Figure 4-5. Linear Feedback Shift Register (LFSR) Tx_clk lfsr_out LFSR Tx_en cipher-text_out TX_bit Figure 4-6. Scrambler Function of KS8910 4-10...

  • Page 38: Descramble Function Of Ks8910

    Line State (ILS) pattern while SIGNAL_DETECT is asserted and the output of the MLT-3 decoder is valid: In the KS8910, the hybrid mode is supported, the descrambler will, therefore, acquire synchronization on receipt of 30 consecutive error-free cipher-text bits of the JK symbol sequence while SIGNAL_DETECT is asserted and the output of the MLT-3 decoder is valid.

  • Page 39: Link Monitor

    (SIGNAL_STATUS = OFF) + (link_control = DISABLE) + (faulting = TRUE) LINK DOWN link_status=FAIL SIGNAL_STATUS = ON HYSTERESIS Start stabilize_timer stabilize_timer_done LINK READY link_status=READY link_control = ENABLE LINKUP link_status=OK link_control = SCAN_FOR_CARRIER Figure 4-8. Link Monitor State Diagram of KS8910 4-12...

  • Page 40: Nrz To Nrzi And Nrzi To Nrz Conversion

    100BASE-TX DIGITAL BLOCKS NRZ TO NRZI AND NRZI TO NRZ CONVERSION An NRZ to NRZI and NRZI to NRZ conversion module is designed into the KS8910 chip.This conversion can be bypassed, and is controllable through a register bit. The NRZ to NRZI module converts the signal from NRZ to NRZI as follows: The converter module samples the input at the center of each bit period.

  • Page 41: Physical Medium Dependent Sublayer

    Preliminary Spec. ver 100BASE-TX DIGITAL BLOCKS KS8910 100/10 Mbps ETHERNET TRANSCEIVER PHYSICAL MEDIUM DEPENDENT SUBLAYER The majority of the PMD is either analog or mixed-signal and is, therefore, not described in this charter, though a resume is given just below. A detailed description of this part of the circuitry can be found in chapter 6 of this document.

  • Page 42: 10 Base-T Digital Blocks

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER 10BASE-T DIGITAL BLOCKS 10 BASE-T DIGITAL BLOCKS OVERVIEW The 10BASE-T Ethernet Interface Transceiver subsystem performs the physical layer signaling (PSL) and Media Attachment Unit (MAU) functions as defined by the IEEE 802.3 specification. It functions as a PLS-only device as an Integrated PLS/MAU (for use with 10BASE-T twisted-pair networks).

  • Page 43: State Diagram Of Jabber Control Function

    Preliminary Spec. ver 10BASE-T DIGITAL BLOCKS KS8910 100/10 Mbps ETHERNET TRANSCEIVER Reset (1)Unjab TimerEq0=‘ 1 ’ JC_IDLE_1w jc_dis_XMIT=’ 0 ’ jc_ci_sqe=’ 0 ’ jc_set_TxMaxTimer=’ 0 ’ jc_clr_TxMaxTimer=’ 0 ’ jc_en_TxMaxTimer=’ 0 ’ JC_UNJAB JC_IDLE jc_set_sr_JabberStatus=’ 0 ’ jc_set_UnJabberStatus=’ 0 ’...

  • Page 44: Sqe Function

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER 10BASE-T DIGITAL BLOCKS SQE FUNCTION The 10BASE-T transceiver supports the signal quality error (SQE) function as shown in Figure 5-3. If SQE register is enabled after every successful transmission on the 10BASE-T network, the 10BASE-T transceiver transmits the SQE signal to the DTE for ten 5 bit times over the internal CI Circuit.

  • Page 45: Collision Detection Function

    Preliminary Spec. ver 10BASE-T DIGITAL BLOCKS KS8910 100/10 Mbps ETHERNET TRANSCEIVER COLLISION DETECTION FUNCTION The collision detection function operates on the twisted-pair side of the interface. A collision is defined as the simul- taneous presence of valid signals on both the TPI circuit and the TPO circuit. The 10BASE-T transceiver reports collisions to the back-end via the COL pin.

  • Page 46: Loopback Function

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER 10BASE-T DIGITAL BLOCKS LOOP-BACK FUNCTION The 10BASE-T Transceiver provides the normal loopback function specified by the 10BASE-T standard for the twisted-pair port. The loopback function operates in conjunction with the transmit function. Data transmitted by the back-end is internally looped back within the 10BASE-T Transceiver from the TXD pin through the Manchester encoder/decoder to the RXD pin and returned to the back-end.
  • Page 47 Preliminary Spec. ver 10BASE-T DIGITAL BLOCKS KS8910 100/10 Mbps ETHERNET TRANSCEIVER MEMO...

  • Page 48: Analog Blocks

    MHz crystal, a reference bias resistor, but the chip loop filters for the transmit and receive PLLs is integrated on chip. 100Mbit/s Digital Blocks 100Mbit/s Analog Blocks Frequency Chip 25Mhz Synthesizer 4B5B Scrambler Transmitter Cat.5 UTP Transformer Adptive Descrambler 5B4B Baseline Restore Equalization Cat.5 UTP Clock Recovery Board Figure 6-1. 100Mbit/s Data Path Block Diagram of KS8910...

  • Page 49: 100Mbit/S Transmit Circuits

    DPLL RX SQ Figure 6-2. Analog Blocks of KS8910 The main transmit analog blocks are the clock generator, the wave shaper, and the driver. The receive blocks include a receive buffer . In addition, the receive circuit detects the presence of on the receive twisted pair and supplies status signals to the auto-negotiation circuit indicating lock detect and signal detect.

  • Page 50: Frequency Synthesizer

    The values of the loading capacitors should be adjusted to match the recommended loading for the crystal used. The recommended crystal is loaded with 15pF capacitors as shown in Figure 6-3. The external crystal and loading capacitors are connected between the XTAL_IN and XTAL_OUT pins of KS8910 . KS8910...

  • Page 51: Transmit Twisted-Pair Driver

    Preliminary Spec. ver 100BASE-TX ANALOG BLOCKS KS8910 100/10 Mbps ETHERNET TRANSCEIVER Clock Dividers The frequency synthesizer is completed by a clock divider circuit that generates the remaining clocks required by the design. The clocks and their uses are summarized in Table 6-1.

  • Page 52: 100Mbit/S Receive Circuits

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER 100BASE-TX ANALOG BLOCKS TPOB 1 CT TPOP 200Ω ±1% Cable 0.1uF 75Ω ±1% 0.1uF TPON Chip Board Figure 6-4. Transmit Twister-Pair Driver and Transmit Transformer Voltage Reference An on-chip band-gap reference calibrates the output voltage swing. This reference generates an on-chip voltage voltage reference with an error of ±2.5%.

  • Page 53: Adaptive Equalizer

    Preliminary Spec. ver 100BASE-TX ANALOG BLOCKS KS8910 100/10 Mbps ETHERNET TRANSCEIVER 1 CT 1 CT TPIP all resistors are 1% 100Ω 0.1uF 75Ω 0.1uF TPIN Chip Board Figure 6-5. Receive Buffer Circuit Configuration ADAPTIVE EQUALIZER High frequency attenuation and group delay variation introduced by the twisted pair degrades the data signal. The adaptive equalizer restores these high frequency components and restores the data to a condition suitable for clock recovery and data slicing.

  • Page 54: 10Mbit/S Transmit Circuits

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER 100BASE-TX ANALOG BLOCKS A differential loop filter is integrated on chip. This loop filter forms a second-order loop. Higher order high frequency poles are added by on-chip filters. The VCO gain is 140MHz/Volt, and the charge pump current is 20uA. The recommended components result in a loop bandwidth of 250KHz and a phase margin of 75 degrees.
  • Page 55 Preliminary Spec. ver 100BASE-TX ANALOG BLOCKS KS8910 100/10 Mbps ETHERNET TRANSCEIVER line termination is performed by the circuit shown in Figure 6-5. RECEIVE CLOCK RECOVERY(20MHZ,DPLL) An on-chip frequency synthesis PLL recovers a 20MHz clock using the frequency reference from receiving data.

  • Page 56: Registers

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER REGISTERS REGISTERS OVERVIEW The register set is used to control and monitor the 10Base-T/100Base-TX Transceiver chip and can be accessed through the MII management interface. All changed bits will become active immediately. That includes the ‘ R eset’ and ‘ R estart Auto-Negotiation’ bits in the Base Mode Control Register, BMCR.

  • Page 57: Register Definitions

    Preliminary Spec. ver REGISTERS KS8910 100/10 Mbps ETHERNET TRANSCEIVER REGISTER DEFINITIONS Table 8-1. Address Mapping Register Name Address(Hex) Initial Value BMCR Base Mode Control Register 0(00h) 0011_0100_0000_0000 BMSR Base Mode Status Register 1(01h) 0111_1000_0000_1001 PHYIDR1 PHY Identification Register #1 2(02h)
  • Page 58 When this bit is set, the PHY Layer does not respond to TXD[3::0], TX_EN, and TX_ER inputs, and it presents a ‘ 0 ’ on its TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3::0], COL and CRS outputs. The KS8910 still responds to internal management transactions. • Power Down...
  • Page 59 Preliminary Spec. ver REGISTERS KS8910 100/10 Mbps ETHERNET TRANSCEIVER • PhyLoop PHY Loopback 1 = Enable loop back mode 0 = Disable loop back mode (default) The loopback function enables MII transmit data to be routed to the MII receive data path. This loopback will go through the PMA and the RX clock will be TX clock.

  • Page 60: Base Mode Status : Register 1

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER REGISTERS BASE MODE STATUS : REGISTER 1 [BMSR] 01h - 100FD 100HD 10FD 10HD Reserved MF Prm Sup AN_Comp Rmt Fault AN_Abt Link _Stat Jab_Det Ext_Cap • Ext_Cap Extended Capability 1 = extended register capabilities (permanently set) 0 = basic register set capabilities only •...

  • Page 61: Phy Identifier 1 : Register 2

    Preliminary Spec. ver REGISTERS KS8910 100/10 Mbps ETHERNET TRANSCEIVER PHY IDENTIFIER 1 : REGISTER 2 [PHYIDR1] 02h OUI_MSB • OUI_MSB OUI Most Significant Bits OUI MOST SIGNIFICANT BITS: This register stores bits 3 to 18 of the OUI (000000h) to bits 15 to 0 of this register respectively. The most significant two bits of the OUI are ignored.

  • Page 62: Auto-Negotiation Advertisement : Register 4

    • 10HalfDup 10Base-T Half Duplex 1 = 10Base-T HALF DUPLEX is supported by the KS8910. 0 = 10Base-T HALF DUPLEX is not supported by the KS8910. • 10FullDup 10Base-T Half Duplex 1 = 10Base-T FULL DUPLEX is supported by the KS8910.

  • Page 63: Auto-Negotiation Link Partner Ability : Register 5

    Preliminary Spec. ver REGISTERS KS8910 100/10 Mbps ETHERNET TRANSCEIVER AUTO-NEGOTIATION LINK PARTNER ABILITY : REGISTER 5 [ANLPAR] 05h Base Page Reserved 100_FD 100_HD 10_FD 10_HD Selector • Selector Protocol Selector =00001: These bits contain the binary encoded protocol selector supported by the Link Partner.

  • Page 64: Auto-Negotiation Expansion : Register 6

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER REGISTERS AUTO-NEGOTIATION EXPANSION : REGISTER 6 [ANER] 06h LP_NP_Able NP_Able Page_RX LP_AN_Able • LP_AN_Able Link Partner AN Able 1 = The Link Partner supports the Auto-Negotiation. 0 = The Link Partner does not support the Auto-Negotiation.

  • Page 65: Auto-Negotiation Next Page Transmit Register : Register 7

    • ACK2 Acknowledge 1 = This KS8910 acknowledges the Reception of a Link Code Word. 0 = This KS8910 does not Acknowledge the Reception of a Link Code Word. Write as ZERO, read don’ t care. • NextPg Next Page Indication...

  • Page 66: 10Base-T Control Register : Register 16

    SQE Test Enable 1 = Enable SQE Test Function. 0 = Disable SQE Test Function(default). When this KS8910 is configured for 10Base-T Full Duplex operation, this bit will be ignored.(The collision/SQE function has no meaning in Full Duplex mode.) •...

  • Page 67: 100Base-Tx Control Register : Register 17

    Preliminary Spec. ver REGISTERS KS8910 100/10 Mbps ETHERNET TRANSCEIVER 100BASE-TX CONTROL REGISTER : REGISTER 17 [TXCR] 11h LPBK BPNRZI BP_4B5B BP_SCR DTMode DHybrid IDLESEL • IDLESEL Select the number of IDLE 00 = 22 IDLE bits (default) Bits for descrambler syn-...

  • Page 68: Map Table Register 0 : Register 19

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER REGISTERS MAP TABLE REGISTER 0 : REGISTER 19 [MPTBLE0] 13h Map_Table • Map_Table Map Table PRF Mux output value of PH~PA is desided by Map_Table[26:0]value. The initial value of the Map_Table[15:0] is 0000 0000 0000 0000.

  • Page 69: Analog Control Register 0 : Register 21

    Preliminary Spec. ver REGISTERS KS8910 100/10 Mbps ETHERNET TRANSCEIVER ANALOG CONTROL REGISTER 0 : REGISTER 21 [ANARC0] 15h QinH ~ QinA PinH ~ PinA • QinA Equalizer HPF s/w The fixed output value of prefilter counter when Use_PQ(Reg(16.1)=1 • PinA Equalizer BPF s/w Thefixed output value of prefilter counter.

  • Page 70: Analog Status Register : Register 23

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER REGISTERS ANALOG STATUS REGISTER : REGISTER 23 [ASR] 17h AnaStat • AnaStat Analog Status Register If Sel_BG(MTPBLE0[11] bit value, 1 = Selection of Band gap reference value. 0 = Selection of prefilter counter output value[PG~PA,QI~QA]...

  • Page 71: 100Base-T Status Register : Register 25

    Preliminary Spec. ver REGISTERS KS8910 100/10 Mbps ETHERNET TRANSCEIVER 100BASE-T STATUS REGISTER : REGISTER 25 [TXSR] 19h Resreved LNKST Reserved • Full Duplex 1 = Full Duplex. 0 = Half Duplex. • LNKST Link status 1 = 100Base-TX link is up.

  • Page 72: Electrical Characteristics

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS This chapter describes the electrical characteristics of KS8910 100/10Mbps Ethernet Transceiver. The information is presented according to the following table of contents. • Absolute Maximum Ratings • Recommaned Operating Ranges •...

  • Page 73: Absolute Maximum Ratings

    Preliminary Spec. ver ELECTRICAL CHARACTERISTICS KS8910 100/10 Mbps ETHERNET TRANSCEIVER ABSOLUTE MAXIMUM RATINGS Table 8-1. Absolute Maximum Ratings (T A = 25 °C) Parameter Symbol Unit Supply Voltage GND-0.3 Operating Tempatature °C Storage Temperature °C NOTE: Absolute Maximum Ratings may cause critical device failure by above table beyond limits.

  • Page 74: D.c Electrical Characteristics

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER ELECTRICAL CHARACTERISTICS D.C ELECTRICAL CHARACTERISTICS MII PADS SPECIFICATION =3.3V ¡ ¾ 10%, T =0 to 125°C(5.0V Tolerant I/O) Table 8-3. MII Pads Specification Parameter Symbol Conditions Unit Input Low Voltage Input High Voltage...

  • Page 75: 10Base-T Transceiver Characteristics

    Preliminary Spec. ver ELECTRICAL CHARACTERISTICS KS8910 100/10 Mbps ETHERNET TRANSCEIVER 10BASE-T TRANSCEIVER CHARACTERISTICS =3.3V ¡ ¾ 10%, T =0 to 125°C(5.0V Tolerant I/O) Table 8-5. 10Base-T Transceiver Specification Parameter Symbol Conditions Unit Normal Threshhold : N TSQ_I Differential Squelch Threshold...

  • Page 76: Timming

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER ELECTRICAL CHARACTERISTICS TIMMING OSC CLOCK FREQUENCY Clk_freq Figure 8-1. Clock Frequency Timing Diagram Table 8-6. Clock Frequency Symbol Conditions Unit Clock Freq Dudy Cycle Clock Period NOTES : 1. Clk Freq switching point is 50% if VDD...

  • Page 77: Mii-Receive Clock Tolerance

    Preliminary Spec. ver ELECTRICAL CHARACTERISTICS KS8910 100/10 Mbps ETHERNET TRANSCEIVER MII-RECEIVE CLOCK TOLERANCE RX_clk Figure 8-3. MII-Receive Clock Tolerance Timing Diagram Table 8-8. MII-Receive Clock Tolerance Symbol Conditions Unit 100M Rx_clk Duty Cycle Rx_clk Period (100Base-TX / MII Interface) Rx_clk Period (10Base-T / MII Interface)

  • Page 78: Mii/10Base-T Transmit Timing

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER ELECTRICAL CHARACTERISTICS MII/10BASE-T TRANSMIT TIMING Tx_clk Tx_en Tx_er TPOP Figure 8-4. MII/10Base-T Transmit Timing Diagram Table 8-9. MII/10Base-T Transmit Timing Symbol Conditions Unit TxD,Tx_en,Tx_er Setup to Tx-clk rise TxD,Tx_en,Tx_er Hold from Tx-clk rise...

  • Page 79: Mii/10Base-T Receive Timing

    Preliminary Spec. ver ELECTRICAL CHARACTERISTICS KS8910 100/10 Mbps ETHERNET TRANSCEIVER MII/10BASE-T RECEIVE TIMING Rx_clk Rx_DV Rx_er TPIP Figure 8-5. MII/10Base-T Receive Timing Diagram Table 8-10. MII/10Base-T Receive Timing Symbol Conditions Unit TPI in to RxD out (Rx latency) RxD,Rx_DV,Rx_er Setup to Rx-clk rise...

  • Page 80: Mii/100Base-Tx Transmit Timing

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER ELECTRICAL CHARACTERISTICS MII/100BASE-TX TRANSMIT TIMING Tx_clk Tx_en TxD[3:0] TPOP Figure 8-6. MII/100Base-TX Transmit Timing Diagram Table 8-11. MII/100Base-TX Transmit Timing Symbol Conditions Unit TxD,Tx_en,Tx_er Setup to Tx-clk rise TxD,Tx_en,Tx_er Hold from Tx-clk rise...

  • Page 81: Mii/100Base-Tx Receive Timing

    Preliminary Spec. ver ELECTRICAL CHARACTERISTICS KS8910 100/10 Mbps ETHERNET TRANSCEIVER MII/100BASE-TX RECEIVE TIMING TPIP RxDV RxD[4:0] Rx_clk Figure 8-7. MII/100Base-TX Receive Timing Diagram Table 8-12. MII/100Base-TX ReceiveTiming Symbol Conditions Unit RXD,RX_EN,RX_RX Setup to RX-CLK rise RXD,RX_EN,RX_ER Hold from RX-CLK rise CRS asserted to RX_DV asserted Receive start of “J”...

  • Page 82: Mii-Management Interface Timing

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER ELECTRICAL CHARACTERISTICS MII-MANAGEMENT INTERFACE TIMING MDIO (output) MDIO (Input) Figure 8-8. MII-Management Interface Timing Diagram Table 8-13. MII-Management Interface Timing Symbol Conditions Unit MDC Minimum High Time MDC Minimum Low Time MDC Period...

  • Page 83: Power On Reset Timming

    Preliminary Spec. ver ELECTRICAL CHARACTERISTICS KS8910 100/10 Mbps ETHERNET TRANSCEIVER POWER ON RESET TIMMING =2.0V Figure 8-9. Power On Reset Timming Diagram Power On Reset Timming Table 9-14. Symbol Conditions Unit Power_On to normal operation 8-12...

  • Page 84: 10Base-T Sqe(Heartbeat) Timing

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER ELECTRICAL CHARACTERISTICS 10BASE-T SQE(Heartbeat) TIMING Tx-clk Tx_en Ready Figure 8-10. 10Base-T (SQE)Heartbeat Timing Diagram Table 8-15. 10Base-T SQE(Heartbeat) Timing Symbol Conditions Unit COL(SQE) Delay after Tx_en off COL(SQE) Pulse duration 8-13...

  • Page 85: 10Base-T Jabber Timing

    Preliminary Spec. ver ELECTRICAL CHARACTERISTICS KS8910 100/10 Mbps ETHERNET TRANSCEIVER 10BASE-T JABBER TIMING Tx_en Figure 8-11. 10Base-T Jabber Timing Diagram Table 8-16. 10Base-T Jabber Timing Symbol Conditions Unit Maximum Transmit time Unjab time 8-14...

  • Page 86: 10Base-T Normal Link Pulse Timing

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER ELECTRICAL CHARACTERISTICS 10BASE-T NORMAL LINK PULSE TIMING TPOP Figure 8-12. 10Base-T Normal Link Pulse Timing Diagram Table 8-17. 10Base-T Normal Link Pulse Timing Symbol Conditions Unit Normal Link Pulse Width (10Base-T) COL Heartbeat assertion duration...

  • Page 87: Auto- Negotiation And Fast Link Pulse Timing

    Preliminary Spec. ver ELECTRICAL CHARACTERISTICS KS8910 100/10 Mbps ETHERNET TRANSCEIVER AUTO- NEGOTIATION AND FAST LINK PULSE TIMING Data Pulse Data Pulse Clock Pulse TPOP FLP Burst FLP Burst FLP Burst TPOP Figure 8-13. Auto-Negotiation and Fast Link Pulse Timing Diagram Table 8-18.

  • Page 88: Nic Applications

    0.1§Þ VSSDR 93C46B 0.068 3VDD 3VDD 3VDD 3VDD 3VDD 3VDD 3VDD VDDTQ 0§Ù 3VDD FDPLX SPSEL ANEN SEL_7W 0.1§Þ 0.1§Þ 0.1§Þ 0.1§Þ VDDTQ 0.068 SW12 SW10 SW11 0§Ù 0.1§Þ 0.1§Þ 10§Þ VSSTQ 0.068 Figure 10-1. KS8910(64-QFP-1414) Schematic Diagram with KS8920...
  • Page 89 Preliminary Spec. ver APPLICATION NOTE KS8910 100/10 Mbps ETHERNET TRANSCEIVER MEMO...

  • Page 90: Mechanical Data

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER MECHANICAL DATA MECHANICAL DATA PACKAGE DIMENSION 64-QFP-1414 PACKAGE Demension in milimeter 17.20 ± 0.30 14.00 ± 0.20 1.00 0.80 0.35 ± 0.10 0.10MAX 0.10MAX 0.80 ± 0.20 Figure 10-1. KS8910 Package Dimension(64-QFP-1414 Type) 10-1...
  • Page 91 Preliminary Spec. ver MECHANICAL DATA KS8910 100/10 Mbps ETHERNET TRANSCEIVER MEMO 10-2...

  • Page 92: Glossary

    Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER APPENDIX APPENDIX GLOSSARY This glossary contains a brief explanation of technical terms, abbreviations, and acronyms used in this document. ETHERNET AND NETWORKING ACRONYMS AND TERMS • 10BASE5 - 500-meter-per-segment Ethernet using half-inch diameter thick coaxial cable. Up to 100 nodes.
  • Page 93 Preliminary Spec. ver APPENDIX KS8910 100/10 Mbps ETHERNET TRANSCEIVER address, ff-ff-ff-ff-ff-ff. • Bundle - A group of signals which have a common set of characteristics and differ only in their information content. • Capture effect - Under heavy load, if at least one of the contending stations is capable of transmitting back-to- back packets continuously, that station can capture the network for long periods.
  • Page 94 Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER APPENDIX • Globally administered address - An Ethernet address whose second bit transmitted, used to distinguish between locally or globally administered addresses, is set to 0, indicating a globally administered (or U, universal) address.
  • Page 95 Preliminary Spec. ver APPENDIX KS8910 100/10 Mbps ETHERNET TRANSCEIVER • LAN - Local Area Network. • Little endian - The byte at memory address 0 contains the least-significant bits. Used by Intel x86, DEC Vax, and DEC PDP-11. • LLC - Logical Link Control layer of LAN CSMA/CD. The upper half of the OSI (which see) reference model data link layer, between the MAC and the network layer.
  • Page 96 Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER APPENDIX • OC12 - 622.08 Mbit/s Optical Carrier 12, SONET Synchronous Transport Signal STS-12. Twelve byte- interleaved STS-1 signals. • OC48 - 2488.32 Mbit/s Optical Carrier 48, SONET Synchronous Transport Signal STS-48. 48 byte-interleaved STS-1 signals.
  • Page 97 Preliminary Spec. ver APPENDIX KS8910 100/10 Mbps ETHERNET TRANSCEIVER • Router - A store-and-forward protocol-dependent device connecting networks that switches packets to the appropriate network. • Runt - A frame that is less than 64 bytes (minFrameSize) long, exclusive of preamble and SFD. Synonym: fragment.
  • Page 98 Preliminary Spec. ver KS8910 100/10 Mbps ETHERNET TRANSCEIVER APPENDIX • TCP - Transmission Control Protocol, a connection-oriented, reliable, full-duplex, virtual circuit byte-stream facility for a user process. Uses IP. Part of the TCP/IP protocol suite. • TCP/IP - Transmission Control Protocol/Internet Protocol, the DARPA Internet protocol suite.
  • Page 99 Preliminary Spec. ver APPENDIX KS8910 100/10 Mbps ETHERNET TRANSCEIVER NOTES...

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