Page 1 DSP56009 24-Bit Digital Signal Processor User’s Manual Motorola, Incorporated Semiconductor Products Sector DSP Division 6501 William Cannon Drive West Austin, TX 78735-8598...
Page 2 Motorola products are not authorized for use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life. Buyer agrees to notify Motorola of any such intended end use whereupon Motorola shall determine availability and suitability of its product or products for the use intended.
Page 3 OVERVIEW SIGNAL DESCRIPTIONS MEMORY, OPERATING MODES, AND INTERRUPTS EXTERNAL MEMORY INTERFACE SERIAL HOST INTERFACE SERIAL AUDIO INTERFACE GENERAL PURPOSE I/O BOOTSTRAP CODE CONTENTS PROGRAMMING REFERENCE APPLICATION EXAMPLES INDEX...
Page 4 OVERVIEW SIGNAL DESCRIPTIONS MEMORY, OPERATING MODES, AND INTERRUPTS EXTERNAL MEMORY INTERFACE SERIAL HOST INTERFACE SERIAL AUDIO INTERFACE GENERAL PURPOSE I/O BOOTSTRAP CODE CONTENTS PROGRAMMING SHEETS APPLICATION EXAMPLES INDEX...
Page 5: Table Of Contents
Manual Conventions ......1-5 DSP56009 FEATURES ......1-6 DSP56009 ARCHITECTURAL OVERVIEW .
Page 6 INTRODUCTION ........3-3 DSP56009 DATA AND PROGRAM MEMORY ... 3-3 3.2.1...
Page 7 (EPS[1:0])—Bits 18–19......4-22 4.2.8.4 EMI One-Shot Refresh (EOSR)—Bit 20 ... 4-22 MOTOROLA DSP56009 User’s Manual...
Page 8 SERIAL HOST INTERFACE INTERNAL ARCHITECTURE . 5-4 5.2.1 SHI Clock Generator......5-5 DSP56009 User’s Manual MOTOROLA...
Page 9 HCSR Host Transmit Data Empty (HTDE)—Bit 15. . . 5-17 5.3.6.14 Host Receive FIFO Not Empty (HRNE)—Bit 17 ..5-18 5.3.6.15 Host Receive FIFO Full (HRFF)—Bit 19 ... 5-18 MOTOROLA DSP56009 User’s Manual...
Page 10 RCS Reserved Bit—Bits 13 and 2 ....6-11 6.3.2.4 RCS Receiver Master (RMST)—Bit 3 ... . 6-11 viii DSP56009 User’s Manual MOTOROLA...
Page 11 SAI Operation During Stop ..... . . 6-24 6.4.2 Initiating a Transmit Session ..... . 6-24 MOTOROLA DSP56009 User’s Manual...
Page 12 TWO CHANNEL COMB FILTER..... . C-7 3-TAP FIR FILTER ....... C-10 DSP56009 User’s Manual MOTOROLA...
Page 13 Figure 2-1 DSP56009 SIgnals ........2-4 Figure 3-1 Memory Maps for PEA = 0, PEB = 0.
Page 14 Figure 5-8 C Start and Stop Events ......5-21 DSP56009 User’s Manual MOTOROLA...
Page 15 GPIO Circuit Diagram ....... . . 7-5 MOTOROLA DSP56009 User’s Manual xiii...
Page 16 On-chip Peripheral Memory Map ......1-16 Table 2-1 DSP56009 Functional Group Signal Allocations ... . . 2-3 Table 2-2 Power Inputs .
Page 17 ECD[7:0] ......... . 4-36 MOTOROLA DSP56009 User’s Manual...
Page 18 GPIO Pin Configuration ....... . 7-4 DSP56009 User’s Manual MOTOROLA...
Page 19: Section 1 Overview
SECTION 1 OVERVIEW MOTOROLA DSP56009 User’s Manual...
Page 20 INTRODUCTION ........1-3 DSP56009 FEATURES ......1-6 DSP56009 ARCHITECTURAL OVERVIEW .
Page 21: Introduction
The versatile, on-board peripherals allow the DSP to be easily connected to almost any other processor with little or no additional logic. The low pin-count (80 pins) allows the DSP56009 to be available in a small, inexpensive package.
Page 22: Manual Organization
• Appendix A—Bootstrap Code Listings lists the code used to bootstrap the DSP56009. • Appendix B—Programming Reference provides a quick reference for the instructions and registers used by the DSP56009. These sheets are provided with the expectation that they be photocopied and used by programmers when programming the registers.
Page 23: Manual Conventions
(see Table 1-1). For example, the RESET pin is active when pulled to ground. Therefore, references to the RESET pin will always have an overbar. Such pins and signals are also said to be “active low” or “low true.” MOTOROLA DSP56009 User’s Manual...
Page 24: Dsp56009 Features
The DSP56009 consists of the DSP56000 core, program and data memory, and peripherals useful for embedded control applications. The following paragraphs provide a list of DSP56009 features and a brief description of its core and peripheral components. • General Features –...
Page 25 – On-chip 4352 × 24-bit Y data RAM and 1792 × 24-bit Y data ROM – On-chip 4608 × 24-bit X data RAM and 3072 × 24-bit X data ROM – On-chip 10240 × 24-bit Program ROM – On-chip 512 × 24-bit Program RAM and 64 × 24-bit bootstrap ROM MOTOROLA DSP56009 User’s Manual...
Page 26: Dsp56009 Architectural Overview
– Four independent, programmable GPIO lines DSP56009 ARCHITECTURAL OVERVIEW The DSP56009 is a member of the 24-bit DSP56000 family. The DSP is composed of the 24-bit DSP56000 core, memory, and a set of peripheral modules as shown in Figure 1-1 on page 1-9. The 24-bit DSP56000 core is composed of a Data ALU, an...
Page 27: Figure 1-1 Dsp56009 Block Diagram
IRQA, IRQB NMI, RESET AA0248k Figure 1-1 DSP56009 Block Diagram The DSP56000 core is dual-natured in that there are two independent, expandable data memory spaces, two address arithmetic units, and a Data ALU that has two accumulators and two shifter/limiters. The duality of the architecture makes it easier to write software for DSP applications.
Page 28: Memory And Peripheral Modules
• Serial Host Interface (SHI)—The SHI provides a fast, yet simple serial interface to connect the DSP56009 to a host processor or to another serial peripheral device. Two serial protocols are available: the Motorola Serial Peripheral Interface (SPI) bus and the Philips Inter Integrated-circuit Control C) bus.
Page 29: Data Arithmetic And Logic Unit (Alu)
Overview DSP56009 Architectural Overview 1.3.2.1 Data Arithmetic and Logic Unit (ALU) The Data Arithmetic and Logic Unit (ALU) has been designed to be fast and provide the capability to process signals having a wide dynamic range. Special circuitry has been provided to facilitate the processing of data overflows and round-off errors. The Data ALU performs all of the arithmetic and logical operations on data operands.
Page 30: Program Control Unit
Overview DSP56009 Architectural Overview AGU registers may be read from or written to via the Global Data Bus as 16-bit operands. The AGU has two modulo arithmetic units that can generate two independent 16-bit addresses every instruction cycle for any two of the XAB, YAB, or PAB.
Page 31: On-Chip Emulation (Once) Port
1.3.3 Memories The three independent memory spaces of the DSP56009—X data, Y data, and program—and their configurations are discussed briefly here. See Section 3 for more detail Memory, Operating Modes, and Interrupts 1.3.3.1...
Page 32 Overview DSP56009 Architectural Overview Table 1-2 Interrupt Starting Addresses and Sources (Continued) Interrupt Interrupt Source Starting Address P:$000A 0–2 IRQB P:$000C Reserved P:$000E Reserved P:$0010 0–2 SAI Left Channel Transmitter if TXIL = 0 P:$0012 0–2 SAI Right Channel Transmitter if TXIL = 0 P:$0014 0–2...
Page 33: Data Memory
Bootstrap ROM The bootstrap ROM occupies locations 0–31 ($0–$1F) and 256–287 ($100–$11F) in two areas in the memory map on the DSP56009. The bootstrap ROM is factory-programmed to perform the bootstrap operation following hardware reset; it either jumps to the user’s ROM starting address (P:$2000) or downloads up to 512 words of user program from either the EMI port or the SHI port (in SPI or I format).
Page 34: External Memory
Program RAM are read-disabled but write-accessible. The contents of the bootstrap ROM are listed in Appendix A. 1.3.3.6 External Memory The DSP56009 does not extend internal memory off chip. However, external memory can be added using the EMI. See Section 4, for a detailed External Memory Interface description of the EMI.
Page 35 Overview DSP56009 Architectural Overview Table 1-4 On-chip Peripheral Memory Map (Continued) Address Register X:$FFF6 EMI Write Offset Register (EWOR) X:$FFF5 Reserved X:$FFF4 Reserved X:$FFF3 SHI Receive FIFO/Transmit Register (HRX/HTX) X:$FFF2 SHI I C Slave Address Register (HSAR) X:$FFF1 SHI Host Control/Status Register (HCSR)
Page 36: External Memory Interface
This interface facilitates the storage of audio samples for digital reverberation algorithms and permits simple implementation of large data delay buffers in external memory. The EMI on the DSP56009 is designed to connect directly to Dynamic RAM (DRAM) of the following sizes: •...
Page 37: Serial Audio Interface (Sai)
Overview DSP56009 Architectural Overview 1.3.4.3 Serial Audio Interface (SAI) The DSP can communicate with other devices through the SAI. The SAI provides a synchronous full-duplex serial port for serial connection with a variety of audio devices such as Analog-to-Digital (A/D) converters, Digital-to-Analog (D/A) converters, Compact Disk (CD) devices, etc.
Page 38 Overview DSP56009 Architectural Overview 1-20 DSP56009 User’s Manual MOTOROLA...
Page 39: Section 2 Signal Descriptions
SECTION 2 SIGNAL DESCRIPTIONS MOTOROLA DSP56009 User’s Manual...
Page 40 GENERAL PURPOSE I/O ......2-21 2.10 ON-CHIP EMULATION (OnCE ) PORT ....2-22 DSP56009 User’s Manual MOTOROLA...
Page 41: Table 2-1 Dsp56009 Functional Group Signal Allocations
Signal Descriptions Signal Groupings SIGNAL GROUPINGS The DSP56009 input and output signals are organized into the nine functional groups, as shown in Table 2-1. The individual signals are illustrated in Figure 2-1. Table 2-1 DSP56009 Functional Group Signal Allocations Detailed...
Page 42: Figure 2-1 Dsp56009 Signals
Tran0 SDO0 MD0–MD7 Tran1 SDO1 MA15/MCS3 Tran2 SDO2 MA16/MCS2/MCAS Port A MA17/MCS1/MRAS External Memory Interface MCS0 GPIO GPIO0–GPIO3 DSCK/OS1 MODC/NMI Mode/Interrupt DSI/OS0 MODB/IRQB OnCE™ Control MODA/IRQA Port Reset RESET 80 signals AA0249G Figure 2-1 DSP56009 SIgnals DSP56009 User’s Manual MOTOROLA...
Page 43: Table 2-2 Power Inputs
Address Bus Ground —GND provides isolated ground for sections of the address bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. MOTOROLA DSP56009 User’s Manual...
Page 44: Table 2-4 Clock And Pll Signals
DSP clock. The PLL output is divided by two to produce a four-phase instruction cycle clock, with the minimum instruction time being two PLL output clock periods. If the PLL is disabled, EXTAL is divided by two to produce the four-phase instruction cycle clock. DSP56009 User’s Manual MOTOROLA...
Page 45: Table 2-5 External Memory Interface (Emi) Signals
PCAP and the other terminal to V . The required capacitor value is specified in the DSP56009 Technical Data sheets. When short lock time is critical, low dielectric absorption capacitors such as polystyrene, polypropylene, or teflon are recommended.
Page 46 If the data bus width is defined as four bits wide, only signals MD0–MD3 are active, while signals MD4–MD7 remain tri-stated. While tri-stated, MD0–MD7 are disconnected from the pins and do not require external pull-ups. DSP56009 User’s Manual MOTOROLA...
Page 47: Table 2-6 Emi Operating States
Driven High Driven High Driven Low Driven High MCS0 — Driven High Driven High Driven High Driven High — Driven High Driven High Driven High Driven High — Driven High Driven High Driven High Driven High MOTOROLA DSP56009 User’s Manual...
Page 48: Table 2-7 Interrupt And Mode Control Signals
While the DSP is in the Stop mode, asserting IRQA gates on the oscillator and, after a clock stabilization delay, enables clocks to the processor and peripherals. Hardware reset causes this input to function as MODA. 2-10 DSP56009 User’s Manual MOTOROLA...
Page 49 However, as the fall time of the interrupt signal increases, the probability that noise on IRQB will generate multiple interrupts also increases. Hardware reset causes this input to function as MODB. MOTOROLA DSP56009 User’s Manual 2-11...
Page 50 However, as the fall time of the interrupt signal increases, the probability that noise on NMI will generate multiple interrupts also increases. Hardware reset causes this input to function as MODC. 2-12 DSP56009 User’s Manual MOTOROLA...
Page 51 RESET signal. For proper hardware reset to occur, the clock must be active, since a number of clock ticks are required for proper propagation of the hardware reset state. MOTOROLA DSP56009 User’s Manual 2-13...
Page 52: Table 2-8 Serial Host Interface (Shi) Signals
Fosc for the SPI mode and for the I C mode. This signal is tri-stated during hardware reset, software reset, or individual reset (no need for external pull-up in this state). 2-14 DSP56009 User’s Manual MOTOROLA...
Page 53 A low-to-high transition of SDA while SCL is high is an unique situation, and is defined as the Stop event. Note: This line is tri-stated during hardware reset, software reset, or individual reset (no need for external pull-up in this state). MOTOROLA DSP56009 User’s Manual 2-15...
Page 54 SS is deasserted, the SHI ignores SCK clocks and keeps the MISO output signal in the high-impedance state. Note: This signal is tri-stated during hardware reset, software reset, or individual reset (no need for external pull-up in this state). 2-16 DSP56009 User’s Manual MOTOROLA...
Page 55 HREQ to proceed to the next transfer. Note: This signal is tri-stated during hardware, software, individual reset, or when the HREQ[1:0] bits (in the HCSR) are cleared (no need for external pull-up in this state). MOTOROLA DSP56009 User’s Manual 2-17...
Page 56: Table 2-9 Serial Audio Interface (Sai) Receiver Signals
Note: SCKR is high impedance if all receivers are disabled (individual reset) and during hardware or software reset, or while the DSP is in the Stop state. 2-18 DSP56009 User’s Manual MOTOROLA...
Page 57 DSP is in the Stop state. While in the high impedance state, the internal input buffer is disconnected from the signal and no external pull-up is necessary. MOTOROLA DSP56009 User’s Manual 2-19...
Page 58: Table 2-10 Serial Audio Interface (Sai) Transmitter Signals
(individual reset), during hardware reset, software reset, or while the DSP is in the Stop state. While in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. 2-20 DSP56009 User’s Manual MOTOROLA...
Page 59: Table 2-11 General Purpose I/O (Gpio) Signals
Note: Hardware reset or software reset configures all the GPIO lines as disconnected (external circuitry connected to these pins may need pull-ups until the pins are configured for operation). MOTOROLA DSP56009 User’s Manual 2-21...
Page 60: Table 2-12 On-Chip Emulation Port Signals
Note: If the OnCE port is in use, an external pull-down resistor should be attached to the DSI/OS0 signal. If the OnCE port is not in use, the resistor is not required. 2-22 DSP56009 User’s Manual MOTOROLA...
Page 61 Note: If the OnCE port is in use, an external pull-down resistor should be attached to the DSCK/OS1 pin. If the OnCE port is not in use, the resistor is not required. MOTOROLA DSP56009 User’s Manual 2-23...
Page 62 OnCE port is ready to receive the data to be written; after the data is written, another acknowledge pulse will be provided. Note: During hardware reset and when idle, the DSO line is held high. 2-24 DSP56009 User’s Manual MOTOROLA...
Page 63 For more information, see Methods Of Entering The Debug Mode in the DSP56000 Family Manual. Note: If the OnCE port is not in use, an external pull-up resistor should be attached to the DR line. MOTOROLA DSP56009 User’s Manual 2-25...
Page 64 Signal Descriptions On-Chip Emulation (OnCE ) Port 2-26 DSP56009 User’s Manual MOTOROLA...
Page 65: And Interrupts
SECTION 3 MEMORY, OPERATING MODES, AND INTERRUPTS...
Page 66 INTRODUCTION ........3-3 DSP56009 DATA AND PROGRAM MEMORY ... 3-3 DSP56009 DATA AND PROGRAM MEMORY MAPS .
Page 67: Table 3-1 Internal Memory Configurations
Introduction INTRODUCTION The DSP56009 program and data memories are independent, and the on-chip data memory is divided into two separate memory spaces, X and Y. There are also two on-chip data ROMs in the X and Y data memory spaces, and a bootstrap ROM that can overlay part of the Program RAM.
Page 68: X Data Rom
The X data ROM occupies locations $2000–$2BFF in the X data memory space. The functions contained in the X data ROM are listed in the DSP56009 Technical Data sheet. For more detailed information, contact the Motorola DSP technical help line.
Page 69: Reserved Memory Spaces
$000005, which is the opcode for the ILLEGAL instruction. DSP56009 DATA AND PROGRAM MEMORY MAPS The memory in the DSP56009 can be mapped into four different configurations according to the PEA and PEB bits in the OMR. Memory maps for each of the four configurations are shown in Figure 3-1, Figure 3-2, Figure 3-3, and Figure 3-4 on the following pages.
Page 70: Figure 3-1 Memory Maps For Pea = 0, Peb = 0
Memory, Operating Modes, and Interrupts DSP56009 Data And Program Memory Maps X Data Y Data Program $FFFF $FFFF $FFFF Internal I/O $FFC0 Reserved $FFBF Reserved Reserved $4800 $2C00 $47FF $2700 $2BFF Internal $26FF Internal Internal $2000 $2000 $2000 $1FFF $1FFF...
Page 71: Figure 3-3 Memory Maps For Pea = 0, Peb = 1
Memory, Operating Modes, and Interrupts DSP56009 Data And Program Memory Maps X Data Y Data Program $FFFF $FFFF $FFFF Internal I/O $FFC0 Reserved $FFBF Reserved Reserved $4800 $2C00 $47FF $2700 $2BFF $26FF Internal Internal Internal $2000 $2000 $2000 $1FFF $1FFF...
Page 72: Dynamic Switching Of Memory Configurations
Memory, Operating Modes, and Interrupts DSP56009 Data And Program Memory Maps 3.3.1 Dynamic Switching of Memory Configurations The internal memory configuration is altered by re-mapping RAM modules from X and Y data memories into program memory space and vise-versa. Data contents of the switched RAM modules are preserved.
Page 73: Internal I/O Memory Map
Although labelled reserved on the DSP56009, the BCR remains active. The BCR is cleared by reset and should remain cleared (i.e., do not write to this location) since the DSP56009 does not make use of the BCR function. MOTOROLA DSP56009 User’s Manual...
Page 74: Table 3-2 Internal I/O Memory Map
Memory, Operating Modes, and Interrupts DSP56009 Data And Program Memory Maps Table 3-2 Internal I/O Memory Map Location Register X: $FFFF Interrupt Priority Register (IPR) X: $FFFE Reserved X: $FFFD PLL Control Register (PCTL) X: $FFFC Reserved X: $FFFB Reserved...
Page 75: Figure 3-5 Operating Mode Register (Omr)
The DSP operating mode bits, MC, MB, and MA, select the operating mode of the DSP56009. These operating modes are described in Section 3.5 Operating Modes on the following page. On hardware reset, MC, MB, and MA are loaded from the external mode select pins MODC, MODB, and MODA, respectively.
Page 76: Program Ram Enable B (Peb)—Bit 3
STOP instruction will allow a faster start up of the DSP. OPERATING MODES The DSP56009 operating modes are defined as described below and summarized in Table 3-3 on page 3-13. The operating modes are latched from pins MODA, MODB, and MODC during reset and can be changed by writing to the OMR.
Page 77: Table 3-3 Operating Modes
Table 3-3 Operating Modes Mode Operating Mode C B A Normal operation, bootstrap disabled Bootstrap from EMI Wake up in Program ROM address $2000 Reserved Reserved Bootstrap from SHI (SPI mode) Reserved Bootstrap from SHI (I C mode) MOTOROLA DSP56009 User’s Manual 3-13...
Page 78: Figure 3-6 Interrupt Priority Register (Address X:$Ffff)
• Bits 10–15 are available for determining IPLs for each peripheral (EMI, SHI, SAI). Two IPL bits are required for each peripheral interrupt group. The interrupt priorities are shown in Table 3-4 and the interrupt vectors are shown in Table 3-5. 3-14 DSP56009 User’s Manual MOTOROLA...
Page 79: Table 3-4 Interrupt Priorities
SHI Receive Overrun Error SHI Transmit Underrun Error SHI Receive FIFO Full SHI Transmit Data SHI Receive FIFO Not Empty EMI EBAR0 Memory Wrap EMI EBAR1 Memory Wrap EMI Read Data Lowest EMI Write Data MOTOROLA DSP56009 User’s Manual 3-15...
Page 80: Table 3-5 Interrupt Vectors
SHI Receive Overrun Error P: $002C SHI Bus Error P: $002E Reserved P: $0030 EMI Write Data P: $0032 EMI Read Data P: $0034 EMI EBAR0 Memory Wrap P: $0036 EMI EBAR1 Memory Wrap P: $0038 Reserved 3-16 DSP56009 User’s Manual MOTOROLA...
Page 81 P: $0046 SAI Left Channel Receiver if RXIL = 1 P: $0048 SAI Right Channel Receiver if RXIL = 1 P: $004A SAI Receiver Exception if RXIL = 1 P: $004C Reserved P: $007E Reserved MOTOROLA DSP56009 User’s Manual 3-17...
Page 82: Figure 3-7 Pll Configuration
• the PLL VCO frequency is divided by the Low Power Divider (LPD) and then used as the internal DSP clock if CSRC is cleared. The DSP56009 PLL multiplication factor is set to 3 during hardware reset, which means that the Multiplication Factor bits (MF[11:0]) in the PCTL are set to $002. The PLL may be disabled (PEN = 0) upon reset by pulling the PINIT pin low.
Page 83: Hardware Reset Operation
HARDWARE RESET OPERATION The processor enters the Reset processing state after the external RESET pin is asserted (hardware reset occurs) for the specified minimum time (See DSP56009 Technical Data sheet). The Reset state: • resets internal peripheral devices by initializing their control registers as described in the individual peripheral sections, •...
Page 84 Memory, Operating Modes, and Interrupts Hardware Reset Operation 3-20 DSP56009 User’s Manual MOTOROLA...
Page 85: External Memory Interface
SECTION 4 EXTERNAL MEMORY INTERFACE MOTOROLA DSP56009 User’s Manual...
Page 86 EMI TIMING........4-50 DSP56009 User’s Manual...
Page 87: Introduction
(EDRR). This will trigger an EMI read operation in which the data is read from the external memory device and is stored in the EDRR. The end of operation is signaled by a status bit or by an interrupt request. MOTOROLA DSP56009 User’s Manual...
Page 88: Emi Features
– Absolute Addressing for program bootstrap and overlays (SRAM or EPROM), and to access external peripherals – Two base registers to handle two delay buffers in parallel – Base-offset address calculation for data-delay buffers – Optional base address post update (increment) DSP56009 User’s Manual MOTOROLA...
Page 89: Table 4-1 Emi Interrupt Vector
P: $0034 EMI EBAR0 Memory Wrap P: $0036 EMI EBAR1 Memory Wrap Table 4-2 EMI Internal Interrupt Priorities Priority Interrupt Source highest EMI EBAR0 Memory Wrap EMI EBAR1 Memory Wrap lowest EMI Read or Write Data MOTOROLA DSP56009 User’s Manual...
Page 90: Figure 4-1 Emi Registers
Offset Register (EOR) (EOR1) X: $FFED (EDRR0) X: $FFEA Data Read Register (EDRR) (EDRR1) X: $FFEE (EDWR0) X: $FFEA Data Write Register (EDWR) (EDWR1) X: $FFEE Data Register Buffer (EDRB) To EMI Data Bus Figure 4-1 EMI Registers DSP56009 User’s Manual MOTOROLA...
Page 91: Emi Base Address Registers (Ebar0 And Ebar1)
0, then in order to write the data sample delayed by N, the value of N should be written into the EWOR. Note: The EWOR is cleared by hardware reset and software reset. MOTOROLA DSP56009 User’s Manual...
Page 92: Emi Offset Register (Eor)
EDRF EDWE EDWR Empty EDRR Full EDRB & EDRR Full EMI Busy Status EMI Data Word Length EMI Read Trigger Select EMI DRAM Timing EMI SRAM Timing EMI Enable AA0402 Figure 4-2 EMI Control/Status Register (ECSR) DSP56009 User’s Manual MOTOROLA...
Page 93: Emi Data Write Registers (Edwr)
(to the right) before being transferred to the EDRR. When writing 12-bit or 20-bit words to external memory via a 4-bit data bus, only the most significant 12 or 20 bits of the EDRB contents are transferred. Similarly, when MOTOROLA DSP56009 User’s Manual...
Page 94: Table 4-3 Emi Memory Accesses And Locations Per Word
Note: EBW is cleared by hardware reset and software reset. Table 4-3 EMI Memory Accesses and Locations Per Word Memory Memory Addressing Bus Width Word Length locations/ accesses/ word word Relative Relative Relative Relative Relative Relative 16 Data/24 Address 4-10 DSP56009 User’s Manual MOTOROLA...
Page 95: Table 4-4 Emi Word Length
The encoding of EWL[2:0] is shown in Table 4-4 . Note: EWL[2:0] are cleared by hardware reset and software reset. Table 4-4 EMI Word Length EWL2 EWL1 EWL0 Word Length 8-bit data word 16-bit data word MOTOROLA DSP56009 User’s Manual 4-11...
Page 96: Table 4-5 Emi Addressing Modes
SRAM Relative MA[14:0] MCS[3:0] n.a. 128 K 0100 DRAM Relative MA[7:0] 64 K 0101 DRAM Relative MA[8:0] 256 K 0110 DRAM Relative MA[9:0] 0111 DRAM Relative MA[10:0] 10xx Reserved DRAM Absolute MA[7:0] 64 K 1100 4-12 DSP56009 User’s Manual MOTOROLA...
Page 97: Table 4-6 Emi Maximum Sram Size
Bus Width Word Length Number of Words 0000 16 K 0000 10,922 0000 0000 6,553 0000 5,461 0000 32 K 0000 12 or 16 16 K 0000 20 or 24 10,922 0001 and 0010 128 K MOTOROLA DSP56009 User’s Manual 4-13...
Page 98: Table 4-7 Emi Maximum Dram Size (Relative Addressing)
12 or 16 64 K 256 K × 4 0101 20 or 24 32 K 2 × 256 K × 4 0101 256 K 2 × 256 K × 4 0101 12 or 16 128 K 4-14 DSP56009 User’s Manual MOTOROLA...
Page 99: Table 4-8 Emi Maximum Dram Size (Absolute Addressing)
2 × 64 K × 4 1100 20 or 24 21,845 256 K × 4 1101 128 K 256 K × 4 1101 87,381 256 K × 4 1101 64 K 256 K × 4 1101 52,428 MOTOROLA DSP56009 User’s Manual 4-15...
Page 100: Emi Increment Ebar After Read (Einr)—Bit 7
Note: EINR is cleared by hardware reset and software reset. 4.2.7.5 EMI Increment EBAR After Write (EINW)—Bit 8 The read/write control bit EMI Increment EBAR after Write (EINW) enables the function of incrementing the contents of the relevant EBARx after a write operation. 4-16 DSP56009 User’s Manual MOTOROLA...
Page 101: Table 4-9 Emi Read/Write Interrupt Select
EBAR0 and EBAR1. The largest word address is reached when the value of the significant bits in EBARx is all 1s. The number of the significant bits in EBARx involved with address generation can be concluded from Table 4-13 MOTOROLA DSP56009 User’s Manual 4-17...
Page 102: Emi Data Write Register Empty (Edwe)—Bit 12
EDRB and the EDRR contain data after memory read operations. EBDF is cleared otherwise. Note: EBDF is cleared by hardware reset, software reset, individual reset, and while the DSP is in the Stop state. 4-18 DSP56009 User’s Manual MOTOROLA...
Page 103: Table 4-10 Emi Dram Timing (Clock Cycles Per Word Transfer)
Relative Relative Relative Relative 12 or 16 Relative Relative Relative 20 or 24 2 × 12 = 24 2 × 8 = 16 Absolute 1 × 12 = 12 1 × 8 = 8 Absolute MOTOROLA DSP56009 User’s Manual 4-19...
Page 104: Table 4-11 Emi Sram Timing (Clock Cycles Per Word Transfer)
12 or 16 5 × (4 + ESTM) 6 × (4 + ESTM) 3 × (4 + ESTM) 20 or 24 Where ESTM is the value of the ESTM[3:0] bits, ranging from 0 to 15 4-20 DSP56009 User’s Manual MOTOROLA...
Page 105: Figure 4-3 Emi Refresh Control Register (Ercr)
ECD7 ECD6 ECD5 ECD4 ECD3 ECD2 ECD1 ECD0 Refresh Rate EREF ERED EOSR EPS1 EPS0 Prescaler Rate One-Shot Refresh Refresh Enable(Debug) Refresh Enable Reserved Bit AA0295 Figure 4-3 EMI Refresh Control Register (ERCR) MOTOROLA DSP56009 User’s Manual 4-21...
Page 106: Emi Refresh Clock Divider (Ecd[7:0])—Bits 0–7
DSP is in the Debug mode independent of the state of EREF. Refresh cycle requests are generated according to the output clock rate of the refresh timer. If ERED is cleared, refresh cycle insertion is disabled when the DSP leaves the Debug mode. 4-22 DSP56009 User’s Manual MOTOROLA...
Page 107: Figure 4-4 Emi Address Generation Block Diagram
Address Register in use can be optionally incremented by one after calculating the word address. Base Address Offset Register C2–C0 Word Address: A23–A0 Relative Addressing Extension Bits Address Format Conversion EMI Address and Chip Select Pins AA0296 Figure 4-4 EMI Address Generation Block Diagram MOTOROLA DSP56009 User’s Manual 4-23...
Page 108: Table 4-12 Relative Addressing Extension Bits
(during a read operation) or unpacking (during a write operation) the data word segment. The accesses proceed from the least significant to the most significant portion of the word. For each of the accesses, the contents of 4-24 DSP56009 User’s Manual MOTOROLA...
Page 109: Sram Relative Addressing
Note: In this addressing mode, if the word length is 20 bits or 24 bits (or 16 bits using 24-bit addressing), it is possible to connect only three SRAMs (and save memory), since MCS0 will not be activated at all. Table 4-13 summarizes the address generation for the SRAM Addressing modes. MOTOROLA DSP56009 User’s Manual 4-25...
Page 110: Table 4-13 Word Address To Physical Address Mapping For Sram
MCS0 = C1 MCS1 = C1 A15 A[13:0], C0 MCS0 = C0 MCS1 = C0 A16 A [14:0] MCS0 = C2 MCS1 = C2 A14 A[12:0], C0, C1 MCS0 = C1 MCS1 = C1 A15 A[13:0], C0 4-26 DSP56009 User’s Manual MOTOROLA...
Page 111: Dram Relative Addressing
0 to 3 extension bits to the right (forming the LSBs of the column addresses). The extension bits are then used to generate the number of column addresses required. Address pins that are not required are kept at the MOTOROLA DSP56009 User’s Manual 4-27...
Page 112: Table 4-14 Word-Address-To-Physical-Address Mapping For Dram
A16 A15 A[13:10] A17 A16 A[14:11] A10 A[6:3] A19 A18 A[16:13] A12 A11 A20 A19 A[17:14] A13 A12 A11 A18 A17 A[15:12] A11 A19 A18 A[16:13] A12 A11 A17 A16 A[14:11] A18 A17 A[15:12] A11 4-28 DSP56009 User’s Manual MOTOROLA...
Page 113: Table 4-15 Address Generation For Dram Relative Addressing
A16 A[15:12] A11 A10 A14 A[13:10] C0 A15 A[14:11] A10 0111 — — A[6:3] A17 A[16:13] A12 A11 A18 A[17:14] A13 A12 A11 A16 A[15:12] A11 A17 A[16:13] A12 A11 A15 A[14:11] C0 A16 A[15:12] A11 MOTOROLA DSP56009 User’s Manual 4-29...
Page 114: Dram Absolute Addressing
DRAM Relative Addressing mode (see Table 4-10 on page 4-19). The DRAM Absolute Addressing modes, however, are useful when 20- or 24-bit data words are used and the wasted memory locations that appear in the DRAM Relative 4-30 DSP56009 User’s Manual MOTOROLA...
Page 115: Table 4-16 Word-To-Physical-Address Mapping For Dram Absolute
This, however, must be assured. The EMI address translation is performed in such a way that it is possible to satisfy these requirements by carefully choosing the base addresses of the different data-delay buffers. MOTOROLA DSP56009 User’s Manual 4-31...
Page 116: Consideration
In order to avoid such a situation the user should set the ERED bit in the ERCR—see Section 4.2.8 EMI Refresh Control Register (ERCR). Refresh cycles will then be initiated by the internal refresh timer according to the ERCR setting. 4-32 DSP56009 User’s Manual MOTOROLA...
Page 117: Figure 4-5 Refresh Timer Functional Diagram
Note: Special attention should be given to cases in which data transfers are performed when the DSP is not polling status bits or receiving EMI interrupts, as the predetermined number of instruction cycles can change due to the insertion of external refresh cycles. MOTOROLA DSP56009 User’s Manual 4-33...
Page 118: Off Line" Refresh
ERCR one-shot refresh enable bit (EOSR), thus inserting one refresh cycle at a time. Care should be taken to ensure that a sufficient number of refresh cycles are executed. Refer to Section 4.4.5 for more details. 4-34 DSP56009 User’s Manual MOTOROLA...
Page 119: Table 4-17 Typical Dram Refresh Timing Requirements
DRAM Refresh 4.4.5 DRAM Refresh Timing Table 4-17 shows the typical refresh requirements of some Motorola DRAM devices. Note that the column “periodic refresh per row” refers to the time between the refresh cycles if refreshing is continuous. Table 4-17 Typical DRAM Refresh Timing Requirements...
Page 120: Table 4-18 Continuous Refresh: Timings And Settings For Eps[1:0] And Ecd[7:0]
0.14% / 0.21% 0.136 µs 66 MHz 8 ms 0.87% / 1.26% 0.197 µs 64 ms 0.11% / 0.16% 81 MHz n.a. 8 ms n.a. n.a. n.a. / 1.03% 0.161 µs 64 ms n.a. / 0.13% 4-36 DSP56009 User’s Manual MOTOROLA...
Page 121: Figure 4-6 Timing Diagram Of A Dram Refresh Cycle (Fast)
Figure 4-6 Timing Diagram of a DRAM Refresh Cycle (Fast) MRAS MCAS During a Refresh Cycle: MCSx, MRD and MWR are deasserted (high), data lines remain high impedance, and address lines remain unchanged. AA0299 Figure 4-7 Timing Diagram Of a DRAM Refresh Cycle (Slow) MOTOROLA DSP56009 User’s Manual 4-37...
Page 122: Emi Operating Considerations
When this occurs: – EBSY is set immediately, – the address calculation is executed at the next I , and – the external access starts at the next cycle after I and ends N I later. 4-38 DSP56009 User’s Manual MOTOROLA...
Page 123: Figure 4-8 Emi Pipeline
IN+1 IN+2 IN+3 –1 read read trig1 EBAR trig2 Core Operation trig3 EDRR comp1 incr1 EMI Operation comp2 incr2 EBSY External Access Data Access # 1 Data Access # 2 AA0300k Figure 4-8 EMI Pipeline MOTOROLA DSP56009 User’s Manual 4-39...
Page 124: Read Data Transfer
The EMI read interrupt can also be generated when both the EDRB and the EDRR are full. In this case, a single fast interrupt service with two MOVEP instructions can read two data words. 4-40 DSP56009 User’s Manual MOTOROLA...
Page 125 ; read the data delayed by OFF_3 ; perform other operations ; or poll EDRF for EDRR full ; or wait a sufficient number of Icyc ; and then, movep X:<<EDRR0,X0 ; read the data delayed by OFF_4 MOTOROLA DSP56009 User’s Manual 4-41...
Page 126 ; triggering from EDRR bclr #ERTS,X:<<ECSR ; set ERTS=0 (turn off EDRR triggering) ; perform other operations ; or poll EDRF for EDRR full ; or wait a sufficient number of Icyc ; and then, 4-42 DSP56009 User’s Manual MOTOROLA...
Page 127: Write-Data Transfer
Data is only transferred from EDWR to the EDRB if the buffer is empty. This feature ensures synchronization between memory writes and DSP writes, as long as the DSP ensures that writes to EDWR occur only if EDWR is empty. MOTOROLA DSP56009 User’s Manual 4-43...
Page 128 ; trigger the next memory write ; transfer perform other operations ; or poll EDWE for EDWR empty ; or wait a sufficient number of Icyc ; and then, movep #DATA_4,X:<<EDWR0 ; trigger the next memory write ; transfer 4-44 DSP56009 User’s Manual MOTOROLA...
Page 129: Emi Operation During Stop
DSP core, after the device exits the Wait state. No control or status bits in the ECSR and ERCR are affected by the Wait state. MOTOROLA DSP56009 User’s Manual 4-45...
Page 130: Figure 4-9 Illustration Of The Data-Delay Structure
(EBAR) Space. Illustration of One data-delay Buffer Illustration of Two Independent Moving Along the Memory Address Range Data-delay Buffers of Different Lengths Region of valid delayed data AA0401 Figure 4-9 Illustration of the Data-Delay Structure 4-46 DSP56009 User’s Manual MOTOROLA...
Page 131 EBARx is incremented, preparing the base address for the next sample. • The contents of EBARx should now be saved to an internal memory location to be used in future accesses to this data-delay buffer. MOTOROLA DSP56009 User’s Manual 4-47...
Page 132: Figure 4-10 Dram For Data Delay Buffers And For Sram For Bootstrap
A[14:0] MD[7:0] DQ[7:0] Absolute SRAM Addressing (MCM60256A) GPIO3 DRAM Relative Addressing A[8:0] (EMI) A[8:0] DQ[3:0] DQ[3:0] DRAM DRAM MCM514256A MCM514256A MRAS MCAS AA0260k Figure 4-10 DRAM for Data Delay Buffers and for SRAM for Bootstrap 4-48 DSP56009 User’s Manual MOTOROLA...
Page 133: Figure 4-11 Sram For Data Delay Buffers And For Bootstrap
DQ7:0 SRAM MDM6206 DQ[7:0] SRAM MDM6206 SRAM SRAM MDM6206 Relative MCM6206 Addressing MCS0 MCS1 MCS2 MCS3 A[14:0] (EMI) DQ[7:0] Absolute SRAM Addressing MCM60256A GPIO3 AA0261k Figure 4-11 SRAM for Data Delay Buffers and for Bootstrap MOTOROLA DSP56009 User’s Manual 4-49...
Page 134: Figure 4-12 Replacing Drams With Srams For Large Arrays
Table 4-20 shows the maximum DSP clock frequencies while using typical DRAM devices: Table 4-20 Maximum DSP Clock Frequencies When Using DRAM DRAM Max Freq EDTM MCM54400A—60 ns 66 MHz 81 MHz MCM54400A—70 ns 50 MHz 81 MHz 4-50 DSP56009 User’s Manual MOTOROLA...
Page 135: Table 4-21 Maximum Dsp Clock Frequencies When Using Sram
Timing Diagrams for DRAM Addressing Modes When operating in the DRAM modes, the timing is defined by the ECSR EDTM bit. The timing is classified as Fast (EDTM = 0) or Slow (EDTM = 1). MOTOROLA DSP56009 User’s Manual 4-51...
Page 136: Figure 4-13 Fast Read Or Write Dram Access Timing-1
Finish last R/W cycle Start new memory cycle Column Address Address Address Address MRAS MCAS Read Valid Data In Data Write Valid Data Out Data AA0403 Figure 4-13 Fast Read or Write DRAM Access Timing—1 4-52 DSP56009 User’s Manual MOTOROLA...
Page 137: Figure 4-14 Fast Read Or Write Dram Access Timing-2
New memory cycle Column Last Column Address Address Address Address Address MRAS MCAS Read Valid Valid Data In Data Data Write Valid Valid Data Out Data Data AA0404 Figure 4-14 Fast Read or Write DRAM Access Timing—2 MOTOROLA DSP56009 User’s Manual 4-53...
Page 138: Figure 4-15 Fast Read Or Write Dram Access Timing-3
New memory cycle Column Last Column Address Address Address Address Address MRAS MCAS Read Valid Valid Data In Data Data Write Valid Valid Data Out Data Data AA0405 Figure 4-15 Fast Read or Write DRAM Access Timing—3 4-54 DSP56009 User’s Manual MOTOROLA...
Page 139: Figure 4-16 Fast Read Or Write Dram Access Timing-4
New memory cycle Column Last Column Address Address Address Address Address MRAS MCAS Read Valid Valid Data In Data Data Write Valid Valid Data Out Data Data AA0406 Figure 4-16 Fast Read or Write DRAM Access Timing—4 MOTOROLA DSP56009 User’s Manual 4-55...
Page 140: Figure 4-17 Fast Read Or Write Dram Access Timing-5
New memory cycle Column Last Column Address Address Address Address Address MRAS MCAS Read Valid Valid Data In Data Data Write Valid Valid Data Out Data Data AA0407 Figure 4-17 Fast Read or Write DRAM Access Timing—5 4-56 DSP56009 User’s Manual MOTOROLA...
Page 141: Figure 4-18 Fast Read Or Write Dram Access Timing-6
New memory cycle Column Last Column Address Address Address Address Address MRAS MCAS Read Valid Valid Data In Data Data Write Valid Valid Data Out Data Data AA0408 Figure 4-18 Fast Read or Write DRAM Access Timing—6 MOTOROLA DSP56009 User’s Manual 4-57...
Page 142: Figure 4-19 Slow Read Or Write Dram Access Timing-1
Finish last R/W cycle 9 10 11 12 New memory cycle Column Address Address Address Address MRAS MCAS Read Valid Data In Data Write Valid Data Out Data AA0409 Figure 4-19 Slow Read or Write DRAM Access Timing—1 4-58 DSP56009 User’s Manual MOTOROLA...
Page 143: Figure 4-20 Slow Read Or Write Dram Access Timing-2
New memory cycle Column Last Column Address Address Address Address Address MRAS MCAS Read Valid Valid Data In Data Data Write Valid Valid Data Out Data Data AA0410 Figure 4-20 Slow Read or Write DRAM Access Timing—2 MOTOROLA DSP56009 User’s Manual 4-59...
Page 144: Figure 4-21 Slow Read Or Write Dram Access Timing-3
New memory cycle Column Last Column Address Address Address Address Address MRAS MCAS Read Valid Valid Data In Data Data Write Valid Valid Data Out Data Data AA0411 Figure 4-21 Slow Read or Write DRAM Access Timing—3 4-60 DSP56009 User’s Manual MOTOROLA...
Page 145: Figure 4-22 Slow Read Or Write Dram Access Timing-4
New memory cycle Column Last Column Address Address Address Address Address MRAS MCAS Read Valid Valid Data In Data Data Write Valid Valid Data Out Data Data AA0412 Figure 4-22 Slow Read or Write DRAM Access Timing—4 MOTOROLA DSP56009 User’s Manual 4-61...
Page 146: Figure 4-23 Slow Read Or Write Dram Access Timing-5
New memory cycle Column Last Column Address Address Address Address Address MRAS MCAS Read Valid Valid Data In Data Data Write Valid Valid Data Out Data Data AA0413 Figure 4-23 Slow Read or Write DRAM Access Timing—5 4-62 DSP56009 User’s Manual MOTOROLA...
Page 147: Figure 4-24 Slow Read Or Write Dram Access Timing-6
New memory cycle Column Last Column Address Address Address Address Address MRAS MCAS Read Valid Valid Data In Data Data Write Valid Valid Data Out Data Data AA0414 Figure 4-24 Slow Read or Write DRAM Access Timing—6 MOTOROLA DSP56009 User’s Manual 4-63...
Page 148: Figure 4-25 Sram Read/Write Timing
Table 4-11 on page 4-20. Repeat One Nibble or Byte Access ESTM + 1 last Address MRAS MCAS Read Valid Data In Data Write Valid Data Out Data AA0415 Figure 4-25 SRAM Read/Write Timing 4-64 DSP56009 User’s Manual MOTOROLA...
Page 149: Serial Host Interface (Shi)
SECTION 5 SERIAL HOST INTERFACE MOTOROLA DSP56009 User’s Manual...
Page 150 CHARACTERISTICS OF THE I C BUS ....5-20 SHI PROGRAMMING CONSIDERATIONS ... . 5-23 DSP56009 User’s Manual MOTOROLA...
Page 151: Introduction
The SHI can also communicate with other serial peripheral devices. The SHI can interface directly to either of two well-known and widely used synchronous serial buses: the Motorola Serial Peripheral Interface (SPI) bus and the Philips Inter-Integrated-circuit Control (I C) bus.
Page 152: Figure 5-1 Serial Host Interface Block Diagram
Global Clock Data Generator SCK/SCL HCKR HCSR MISO/SDA Controller Logic MOSI/HA0 Control INPUT/OUTPUT Shift Register Logic (IOSR) SS/HA2 HREQ (FIFO) Slave Address Recognition Unit (SAR) HSAR 24 BIT AA0416 Figure 5-1 Serial Host Interface Block Diagram DSP56009 User’s Manual MOTOROLA...
Page 153: Figure 5-2 Shi Clock Generator
• Host side—see Figure 5-3 below and Section 5.3.1 on page 5-8 • DSP side—see Figure 5-4 on page 5-6 and Sections 5.3.2 on page 5-8 through 5.3.6 on page 5-13 for detailed information I/O Shift Register (IOSR) IOSR AA0418 Figure 5-3 SHI Programming Model—Host Side MOTOROLA DSP56009 User’s Manual...
Page 154 Serial Host Interface Serial Host Interface Programming Model DSP56009 User’s Manual MOTOROLA...
Page 155: Table 5-1 Shi Interrupt Vectors
SHI Bus Error Table 5-2 SHI Internal Interrupt Priorities Priority Interrupt Highest SHI Bus Error SHI Receive Overrun Error SHI Transmit Underrun Error SHI Receive FIFO Full SHI Transmit Data Lowest SHI Receive FIFO Not Empty MOTOROLA DSP56009 User’s Manual...
Page 156: Figure 5-5 Shi I/O Shift Register (Iosr)
In the single-byte data transfer mode the most significant byte of the HTX is transmitted; in the double-byte mode the two most significant bytes, and in the triple-byte mode all the HTX is transferred. DSP56009 User’s Manual MOTOROLA...
Page 157: Shi Host Receive Data Fifo (Hrx)—Dsp Side
The SHI Clock Control Register (HCKR) is a 24-bit read/write register that controls the SHI clock generator operation. The HCKR bits should be modified only while the SHI is in the individual reset state (HEN = 0 in the HCSR). MOTOROLA DSP56009 User’s Manual...
Page 158: Figure 5-6 Spi Data-To-Clock Timing Diagram
Figure 5-6 SPI Data-To-Clock Timing Diagram The Clock Phase (CPHA) bit controls the relationship between the data on the MISO and MOSI pins and the clock produced or received at the SCK pin. This control bit is 5-10 DSP56009 User’s Manual MOTOROLA...
Page 159: Hckr Prescaler Rate Select (Hrs)—Bit 2
HCKR Prescaler Rate Select (HRS)—Bit 2 The HRS bit controls a prescaler in series with the clock generator divider. This bit is used to extend the range of the divider when slower clock rates are desired. When MOTOROLA DSP56009 User’s Manual 5-11...
Page 160: Table 5-3 Shi Noise Reduction Filter Mode
When HFM1 = 1 and HFM0 = 0, the narrow-spike-tolerance filter mode is selected. In this mode the filters eliminate spikes with durations of up to 20ns. This mode is suitable for use in mildly noisy environments and imposes some limitations on the maximum achievable bit-rate transfer. 5-12 DSP56009 User’s Manual MOTOROLA...
Page 161: Shi Control/Status Register (Hcsr)—Dsp Side
When HI C is cleared, the SHI operates in the SPI mode. When HI C is set, the SHI operates in the I C mode. HI C affects the functionality of the SHI pins as MOTOROLA DSP56009 User’s Manual 5-13...
Page 162: Table 5-4 Shi Data Size
Section 5.3.6.17 Host Bus Error (HBER)—Bit 21). When configured as an I C Master, the SHI controls the I C bus by generating Start events, clock pulses, and Stop events for transmission and reception of serial data. It is 5-14 DSP56009 User’s Manual MOTOROLA...
Page 163: Table 5-5 Hreq Function In Shi Slave Modes
ACK on the last byte. As a result, the slave transmitter must release the SDA line to allow the master to generate the Stop event. If the SHI completes receiving a word and the HRX FIFO is full, the clock will be MOTOROLA DSP56009 User’s Manual 5-15...
Page 164: Hcsr Bus-Error Interrupt Enable (Hbie)—Bit 10
HRNE and HRFF (bits 17 and 19, see below) status bits must be polled to determine if there is data in the receive FIFO. If HRIE[1:0] are not cleared, receive interrupts will be generated according to Table 5-6. 5-16 DSP56009 User’s Manual MOTOROLA...
Page 165: Table 5-6 Hcsr Receive Interrupt Enable Bits
DSP. HTDE is set when the data word is transferred from HTX to the shift register, except for a special case in SPI Master mode when CPHA = 0 (see HCKR). When operating in the SPI Master mode with MOTOROLA DSP56009 User’s Manual 5-17...
Page 166: Host Receive Fifo Not Empty (Hrne)—Bit 17
SS is asserted; in this case, transmission is suspended at the end of transmission of the current word. HBER is cleared only by hardware reset, software reset, SHI individual reset, and during the Stop state. 5-18 DSP56009 User’s Manual MOTOROLA...
Page 167: Hcsr Host Busy (Hbusy)—Bit 22
SS line should be held high. If the SS line is driven low when the SHI is in SPI Master mode, a bus error will be generated (the HCSR HBER bit will be set). MOTOROLA DSP56009 User’s Manual 5-19...
Page 168: Overview
Changes in the data line when the clock line is high will be interpreted as control signals (see Figure 5-7). Data Line Change Stable: of Data Data Valid Allowed AA0422 Figure 5-7 I C Bit Transfer 5-20 DSP56009 User’s Manual MOTOROLA...
Page 169: Figure 5-8 I 2 C Start And Stop Events
The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge-related clock pulse (see Figure 5-9). MOTOROLA DSP56009 User’s Manual 5-21...
Page 170: Figure 5-9 Acknowledgment On The I 2 C Bus
(this feature is not supported by the SHI when operating as an I C master device). This method is also used to provide indivisible data transfers. Various combinations of read/write formats are illustrated in Figure 5-10 and Figure 5-11. 5-22 DSP56009 User’s Manual MOTOROLA...
Page 171: Figure 5-10 I
SHI may communicate with an external device by receiving and/or transmitting data. Before changing the SHI operational mode, an SHI individual reset should be generated by clearing the HEN bit. The following paragraphs describe programming considerations for each operational mode. MOTOROLA DSP56009 User’s Manual 5-23...
Page 172: Spi Slave Mode
The HREQ line may be used to interrupt the external master device. Connecting the HREQ line between two SHI-equipped DSPs, one operating as an SPI master device and the other as an SPI slave device, enables full hardware handshaking if operating with CPHA = 1. 5-24 DSP56009 User’s Manual MOTOROLA...
Page 173: Spi Master Mode
The HRX FIFO contains valid receive data, which may be read by the DSP, if the HRNE status bit is set. Note: Motorola recommends that an SHI individual reset (HEN cleared) be generated before beginning data reception in order to reset the receive FIFO to its initial (empty) state, such as when switching from transmit to receive data.
Page 174 R/W bit of the received slave device address byte has been cleared. Following a receive initiation, data in the SDA line is shifted into IOSR MSB first. Following each received byte, an acknowledge (ACK = 0) is sent at the 5-26 DSP56009 User’s Manual MOTOROLA...
Page 175 I C frame so that they fit in a complete number of words. For this purpose, the slave device address byte does not count as part of the data, and therefore, it is treated separately. MOTOROLA DSP56009 User’s Manual 5-27...
Page 176 Note: The slave address byte should be located in the high portion of the data word, whereas the middle and low portions are ignored. Only one byte (the slave address byte) will be shifted out, independent of the word length defined by the HM0–HM1 bits. 5-28 DSP56009 User’s Manual MOTOROLA...
Page 177 As a result, the last byte of the next received data word is not acknowledged, the slave transmitter releases the SDA line, and the SHI generates the Stop event and terminates the session. MOTOROLA DSP56009 User’s Manual 5-29...
Page 178 HTX are empty, the SHI will suspend the serial clock until new data is written into HTX (when the SHI proceeds with the transmit session) or HIDLE is set (the SHI reactivates the clock to generate the Stop event and terminate the transmit session). 5-30 DSP56009 User’s Manual MOTOROLA...
Page 179: Shi Operation During Stop
• The HCSR status bits and the transmit/receive paths are reset to the same state produced by hardware reset or software reset. • The HCSR and HCKR control bits are not affected. Note: Motorola recommends that the SHI be disabled before entering the Stop state. MOTOROLA DSP56009 User’s Manual...
Page 180 Serial Host Interface SHI Programming Considerations 5-32 DSP56009 User’s Manual MOTOROLA...
Page 181: Serial Audio Interface (Sai)
SECTION 6 SERIAL AUDIO INTERFACE MOTOROLA DSP56009 User’s Manual...
Page 182 INTRODUCTION ........6-3 SERIAL AUDIO INTERFACE INTERNAL ARCHITECTURE 6-4 SERIAL AUDIO INTERFACE PROGRAMMING MODEL . . . 6-8 PROGRAMMING CONSIDERATIONS ....6-24 DSP56009 User’s Manual MOTOROLA...
Page 183: Introduction
• Maximum external serial clock rate equal to one third of the DSP core clock • Separate transmit and receive sections • Master or Slave operating modes • Three synchronized data transmission lines • Two synchronized data reception lines • Double-buffered MOTOROLA DSP56009 User’s Manual...
Page 184: Figure 6-1 Sai Baud-Rate Generator Block Diagram
RMST = 0 RClock SCKR RMST = 1 Internal Clock RMST Prescale Divider Divide Divide By 1 Divide By 1 By 2 Divide By 8 Divide By 256 AA0427k PM0–PM7 Figure 6-1 SAI Baud-Rate Generator Block Diagram DSP56009 User’s Manual MOTOROLA...
Page 185: Figure 6-2 Sai Receive Section Block Diagram
32 bits. This is done by disabling eight data shifts at the beginning/end of the data word transfer, according to the RDWT bit in the RCS register. These shift registers cannot be directly accessed by the DSP. MOTOROLA DSP56009 User’s Manual...
Page 186: Sai Transmit Section Overview
TRDE and TLDE are cleared, and the transmit section external pins, Word Select Transmit (WST) and Serial Clock Transmit (SCKT), are tri-stated. The transmitter section is illustrated in Figure 6-3 . DSP56009 User’s Manual MOTOROLA...
Page 187: Figure 6-3 Sai Transmit Section Block Diagram
This is done by enabling eight data shifts at the beginning/end of the data word transfer, according to the TDWE bit in the TCS register. These shift registers cannot be directly accessed by the DSP. MOTOROLA DSP56009 User’s Manual...
Page 188: Figure 6-4 Sai Registers
RXIL bit in the Receive Control Status (RCS) register. The interrupt vector locations for the SAI are shown in Table 6-1 . The interrupts generated by the SAI are prioritized as shown in Table 6-2 . DSP56009 User’s Manual MOTOROLA...
Page 189: Table 6-1 Sai Interrupt Vector Locations
When read by the DSP, the BRC appears on the two low-order bytes of the 24-bit word, and the high-order byte is read as 0s. The BRC is cleared during hardware reset and software reset. MOTOROLA DSP56009 User’s Manual...
Page 190: Prescale Modulus Select (Pm[7:0])—Bits 7–0
The read/write Receiver 0 Enable (R0EN) control bit enables the operation of SAI Receiver 0. When R0EN is set, Receiver 0 is enabled. When R0EN is cleared, Receiver 0 is disabled. If both R0EN and R1EN are cleared, the receiver section is disabled, 6-10 DSP56009 User’s Manual MOTOROLA...
Page 191: Table 6-3 Receiver Word Length Control
16 most significant bits of the receive data register, independent of the Receiver data shift Direction bit (RDIR, see below), while the 8 least significant bits of the receive data register are cleared. If a 32-bit word length is selected, 8 bits are MOTOROLA DSP56009 User’s Manual 6-11...
Page 192: Figure 6-5 Receiver Data Shift Direction (Rdir) Programming
Left data word and WSR low identifies the Right data word (see Figure 6-6 ). The RLRS bit is cleared during hardware reset and software reset. RLRS = 0 Right Left Left Right RLRS = 1 AA0432 Figure 6-6 Receiver Left/Right Selection (RLRS) Programming 6-12 DSP56009 User’s Manual MOTOROLA...
Page 193: Figure 6-7 Receiver Clock Polarity (Rckp) Programming
WSR occurs one serial clock cycle earlier (together with the last bit of the previous data word), as required by the I S format (see Figure 6-8 ). The RREL bit is cleared during hardware reset and software reset. MOTOROLA DSP56009 User’s Manual 6-13...
Page 194: Figure 6-8 Receiver Relative Timing (Rrel) Programming
1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 SCKR Left Right RDWT = 0 RDWT = 1 AA0435k Figure 6-9 Receiver Data Word Truncation (RDWT) Programming 6-14 DSP56009 User’s Manual MOTOROLA...
Page 195: Rcs Receiver Interrupt Enable (Rxie)—Bit 11
Channel Receiver, the Right Channel Receiver and the Receiver Exception interrupt vectors are located in program addresses $46, $48, and $4A, respectively. The RXIL bit is cleared during hardware reset and software reset. Refer to Table 6-1 on page 6-9. MOTOROLA DSP56009 User’s Manual 6-15...
Page 196: Rcs Receiver Left Data Full (Rldf)—Bit 14
RXIE is set, an interrupt request will be issued when RRDF is set. The vector of the interrupt request will depend on the state of the receive overrun condition. The RRDF bit is cleared during hardware reset and software reset. 6-16 DSP56009 User’s Manual MOTOROLA...
Page 197: Sai Receive Data Registers (Rx0 And Rx1)
SDO1 line is set to high level. If T0EN, T1EN and T2EN are cleared, the SAI transmitter section is disabled and enters the individual reset state. The T1EN bit is cleared during hardware reset and software reset. MOTOROLA DSP56009 User’s Manual 6-17...
Page 198: Table 6-4 Transmitter Word Length
When TDIR is cleared, transmit data is shifted out MSB first. When TDIR is set, the data is shifted out LSB first (see Figure 6-10). The TDIR bit is cleared during hardware reset and software reset. 6-18 DSP56009 User’s Manual MOTOROLA...
Page 199: Figure 6-10 Transmitter Data Shift Direction (Tdir) Programming
SDOx lines change synchronously with the positive edge of the clock, and are considered valid during negative transitions of the clock (see Figure 6-12). The TCKP bit is cleared during hardware reset and software reset. MOTOROLA DSP56009 User’s Manual 6-19...
Page 200: Figure 6-12 Transmitter Clock Polarity (Tckp) Programming
The read/write Transmitter Data Word Expansion (TDWE) control bit selects the method used to expand a 24-bit data word to 32 bits during transmission. When TDWE is cleared, after transmitting the 24-bit data word from the transmit data 6-20 DSP56009 User’s Manual MOTOROLA...
Page 201: Figure 6-14 Transmitter Data Word Expansion (Tdwe) Programming
TRDE = 1. The transmit data registers should be loaded with the right data words. 3. Transmit interrupt with exception (underrun) is generated when TXIE = 1, TLDE = 1, and TRDE = 1. This means that old data is being retransmitted. MOTOROLA DSP56009 User’s Manual 6-21...
Page 202: Tcs Transmitter Interrupt Location (Txil)—Bit 12
TCS register, followed by writing the transmit data registers of the enabled transmitters. If TXIE is set, an interrupt request will be issued when TLDE is set. The vector of the interrupt request will depend on the state of the transmit underrun 6-22 DSP56009 User’s Manual MOTOROLA...
Page 203: Tcs Transmitter Right Data Empty (Trde)—Bit 15
The transmit data registers should be written with left channel and right channel data alternately. The first word to be transmitted, after enabling the operation of the respective transmitter, will be the left channel word. MOTOROLA DSP56009 User’s Manual 6-23...
Page 204: Programming Considerations
When the condition arises for the receive interrupt to occur, the same interrupt service routine may be used to read data from the receiver section and to write data to the transmitter section. 6-24 DSP56009 User’s Manual MOTOROLA...
Page 205: Sai State Machine
During a data word transfer (i.e., before completion), all transitions in WSR/WST are ignored. After completion of a data word transfer the SAI stops shifting data in and out until the next correct WSR/WST transition is detected. MOTOROLA DSP56009 User’s Manual 6-25...
Page 206 WSR/WST transition, the data bits being received are ignored and no data is transmitted. These characteristics can be used to disable reception or transmission of undesired data words by keeping SCKR (SCKT) running freely and gating WSR/WST for a certain number of bit-clock cycles. 6-26 DSP56009 User’s Manual MOTOROLA...
Page 207: General Purpose Input/Output
SECTION 7 GENERAL PURPOSE INPUT/OUTPUT MOTOROLA DSP56009 User’s Manual...
Page 208 GPIO PROGRAMMING MODEL ..... . 7-3 GPIO REGISTER (GPIOR) ......7-3 DSP56009 User’s Manual MOTOROLA...
Page 209: Figure 7-1 Gpio Control/Data Register
GPIOR are used to read from or write to the GPIO pins. Hardware reset and software reset clear all the bits in GPIOR. The GPIOR bits are described in the following paragraphs. MOTOROLA DSP56009 User’s Manual...
Page 210: Table 7-1 Gpio Pin Configuration
The read/write GPIO Control bits (GC[3:0]) select the type of output buffer for each of the GPIO[3:0] pins when the pins are defined as outputs, and select whether or not the input buffer is connected to the pin when the pin is defined as an input. DSP56009 User’s Manual MOTOROLA...
Page 211: Figure 7-2 Gpio Circuit Diagram
GPIOx pin output buffer is defined as an open-drain type (see Table 7-1 and Figure 7-2 ). The GC[3:0] bits are cleared during hardware reset and software reset. Buffer GD0-GD3 Control* See Table 7-1 GPIO Pin Configuration. AA0442k Figure 7-2 GPIO Circuit Diagram MOTOROLA DSP56009 User’s Manual...
Page 212 General Purpose Input/Output GPIO Register (GPIOR) DSP56009 User’s Manual MOTOROLA...
Page 213 APPENDIX A BOOTSTRAP ROM CONTENTS 0100101001011010 1010101010110110 1010101010010111 0100101001011010 0101001010010111 1010101010110110 1000101010100100 1010101010010111 0100010101011101 0101001010010111 1000101010100100 0100010101011101 MOTOROLA DSP56009 User’s Manual...
Page 214 BOOTSTRAP PROGRAM LISTING ....A-4 BOOTSTRAP FLOW CHART ......A-7 DSP56009 User’s Manual MOTOROLA...
Page 215: A.1 Introduction
24-bits long and are received through the SHI. The SHI operates in the Slave mode, with the 10-word FIFO enabled, and with the HREQ pin enabled for receive operation. The OnCE port is enabled by the bootstrap code. The bootstrap program listing is shown on the following page. MOTOROLA DSP56009 User’s Manual...
Page 216: A.3 Bootstrap Program Listing
Bootstrap ROM Contents BOOTSTRAP PROGRAM LISTING ; BOOTSTRAP CODE FOR DSP56009—(C) Copyright 1995 Motorola Inc. ; Revised April 16, 1995. ; Bootstrap through EMI, SHI-SPI and SHI-I2C, according to op-modes MC:MB:MA. ; Occupies 32 words of bootstrap ROM in the address range P:$0-P:$1F $fffe ;...
Page 217 ; for transfer is 24 bits. The SHI operates in the SPI or in the ; IIC mode, according to the Bootstrap mode. shild jclr #mb,omr,shi_loop; ;If MC:MB:MA = 101, then bset #hi2c,r1 ; IIC (HI2C = 1) MOTOROLA DSP56009 User’s Manual...
Page 218 ; set operating mode to 0 ; (and trigger an exit from ; Bootstrap mode). movep a1,x:bcr ; Delay needed for Op. Mode ; change used to clear BCR. (r0) ; Then go to destination address. DSP56009 User’s Manual MOTOROLA...
Page 219: A.4 Bootstrap Flow Chart
OnCE Enabled Mode A? Mode C? Mode B? Download Download Download SHI/SPI SHI/I Switch to Switch to Normal Mode & Normal Mode & Go to P:$0 Go to P:$2000 AA0443k Figure A-1 Bootstrap Flow Chart MOTOROLA DSP56009 User’s Manual...
Page 220 Bootstrap ROM Contents DSP56009 User’s Manual MOTOROLA...
Page 221: Appendix B Programming Reference
APPENDIX B PROGRAMMING REFERENCE MOTOROLA DSP56009 User’s Manual...
Page 222 INSTRUCTION SET SUMMARY..... . B-3 PROGRAMMING SHEETS ......B-3 DSP56009 User’s Manual MOTOROLA...
Page 223: B.1 Introduction
Table B-3 on page B-7 summarizes the instruction set. For more detailed information about the instructions, consult the DSP56000 Family Manual . PROGRAMMING SHEETS Figure B-2 on page B-14 through Figure B-17 on page B-29 are programming sheets for the complete set of programmable registers on the DSP. MOTOROLA DSP56009 User’s Manual...
Page 224 = Unused and reserved. Read as a random number. To ensure future compatibility, do not write to these registers. = Unused and reserved. Consult the appropriate chapter for information on how to ensure future compatibility. Figure B-1 On-chip Peripheral Memory Map DSP56009 User’s Manual MOTOROLA...
Page 225 Reserved P:$003E Illegal Instruction P: $0040 0–2 SAI Left Channel Transmitter if TXIL = 1 P: $0042 0–2 SAI Right Channel Transmitter if TXIL = 1 P: $0044 0–2 SAI Transmitter Exception if TXIL = 1 MOTOROLA DSP56009 User’s Manual...
Page 226 SHI Bus Error SHI Receive Overrun Error SHI Transmit Underrun Error SHI Receive FIFO Full SHI Transmit Data SHI Receive FIFO Not Empty EMI EBAR0 Memory Wrap EMI EBAR1 Memory Wrap EMI Read Data Lowest EMI Write Data DSP56009 User’s Manual MOTOROLA...
Page 227 * indicates that the bit may be set according to the definition, depending on parallel move conditions ? indicates that the bit is set according to a special definition. See the instruction descriptions in Appendix A of the DSP56000 Family Manual (DSP56KFAMUM/AD) 0 indicates that the bit is cleared MOTOROLA DSP56009 User’s Manual...
Page 228 * indicates that the bit may be set according to the definition, depending on parallel move conditions ? indicates that the bit is set according to a special definition. See the instruction descriptions in Appendix A of the DSP56000 Family Manual (DSP56KFAMUM/AD) 0 indicates that the bit is cleared DSP56009 User’s Manual MOTOROLA...
Page 229 * indicates that the bit may be set according to the definition, depending on parallel move conditions ? indicates that the bit is set according to a special definition. See the instruction descriptions in Appendix A of the DSP56000 Family Manual (DSP56KFAMUM/AD) 0 indicates that the bit is cleared MOTOROLA DSP56009 User’s Manual...
Page 230 * indicates that the bit may be set according to the definition, depending on parallel move conditions ? indicates that the bit is set according to a special definition. See the instruction descriptions in Appendix A of the DSP56000 Family Manual (DSP56KFAMUM/AD) 0 indicates that the bit is cleared B-10 DSP56009 User’s Manual MOTOROLA...
Page 231 * indicates that the bit may be set according to the definition, depending on parallel move conditions ? indicates that the bit is set according to a special definition. See the instruction descriptions in Appendix A of the DSP56000 Family Manual (DSP56KFAMUM/AD) 0 indicates that the bit is cleared MOTOROLA DSP56009 User’s Manual B-11...
Page 232 * indicates that the bit may be set according to the definition, depending on parallel move conditions ? indicates that the bit is set according to a special definition. See the instruction descriptions in Appendix A of the DSP56000 Family Manual (DSP56KFAMUM/AD) 0 indicates that the bit is cleared B-12 DSP56009 User’s Manual MOTOROLA...
Page 233 * indicates that the bit may be set according to the definition, depending on parallel move conditions ? indicates that the bit is set according to a special definition. See the instruction descriptions in Appendix A of the DSP56000 Family Manual (DSP56KFAMUM/AD) 0 indicates that the bit is cleared MOTOROLA DSP56009 User’s Manual B-13...
Page 234 Reset = $0300 Mode Register (MR) Condition Code Register (CCR) = Reserved, write as 0 Note: The operation and function of the Status Register is detailed in the DSP56000 Family Manual Figure B-2 Status Register (SR) B-14 DSP56009 User’s Manual MOTOROLA...
Page 235 Programming Reference Date: Application: Programmer: Sheet 2 of 4 Figure B-3 Interrupt Priority Register (IPR) MOTOROLA DSP56009 User’s Manual B-15...
Page 236 Programming Reference Date: Application: Programmer: Sheet 3 of 4 Figure B-4 Operating Mode Register (OMR) B-16 DSP56009 User’s Manual MOTOROLA...
Page 237 Programming Reference Date: Application: Programmer: Sheet 4 of 4 Figure B-5 PLL Control Register (PCTL) MOTOROLA DSP56009 User’s Manual B-17...
Page 238 Programming Reference Date: Application: Programmer: Sheet 1 of 4 Figure B-6 EMI Control/Status Register (ECSR) B-18 DSP56009 User’s Manual MOTOROLA...
Page 239 Programming Reference Date: Application: Programmer: Sheet 2 of 4 Figure B-7 EMI Base Address and Offset Registers MOTOROLA DSP56009 User’s Manual B-19...
Page 240 Programming Reference Date: Application: Programmer: Sheet 3 of 4 Figure B-8 EMI Data Registers B-20 DSP56009 User’s Manual MOTOROLA...
Page 241 Programming Reference Date: Application: Programmer: Sheet 4 of 4 Figure B-9 EMI Refresh Control Register (ERCR) MOTOROLA DSP56009 User’s Manual B-21...
Page 242 Programming Reference Date: Application: Programmer: Sheet 1 of 3 Figure B-10 SHI Slave Address and Clock Control Registers B-22 DSP56009 User’s Manual MOTOROLA...
Page 243 Programming Reference Date: Application: Programmer: Sheet 2 of 3 Figure B-11 SHI Host Data Registers MOTOROLA DSP56009 User’s Manual B-23...
Page 244 Programming Reference Date: Application: Programmer: Sheet 3 of 3 Figure B-12 SHI Control/Status Register (HCSR) B-24 DSP56009 User’s Manual MOTOROLA...
Page 245 15 14 13 12 11 10 RRDF RLDF RXIL RXIE RDWT RREL RCKP RLRS RDIR RWL1 RWL0 RMST R1EN R0EN Receiver Control/Status Register (RCS) X:$FFE1 Reset = $0000 = Reserved, write as 0 Figure B-13 SAI Receiver Control/Status Register (RCS) MOTOROLA DSP56009 User’s Manual B-25...
Page 246 TLDE TXIL TXIE TDWE TREL TCKP TLRS TDIR TWL1 TWL0 TMST T2EN T1EN T0EN = Reserved, write as 0 Transmitter Control/ Status Register (TCS) X:$FFE4 Reset = $0000 Figure B-14 SAI Transmitter Control/Status Register (TCS) B-26 DSP56009 User’s Manual MOTOROLA...
Page 247 Programming Reference Date: Application: Programmer: Sheet 3 of 4 Figure B-15 SAI Baud Rate Control and Receive Data Registers MOTOROLA DSP56009 User’s Manual B-27...
Page 248 Programming Reference Date: Application: Programmer: Sheet 4 of 4 Figure B-16 SAI Transmit Data Registers B-28 DSP56009 User’s Manual MOTOROLA...
Page 249 Programming Reference Date: Application: Programmer: Sheet 1 of 1 Figure B-17 GPIO Control/Data Register (GPIOR) MOTOROLA DSP56009 User’s Manual B-29...
Page 250 Programming Reference B-30 DSP56009 User’s Manual MOTOROLA...
Page 251: Appendix C Application Examples
APPENDIX C APPLICATION EXAMPLES MOTOROLA DSP56009 User’s Manual...
Page 252 TWO CHANNEL COMB FILTER ..... . C-7 3-TAP FIR FILTER ....... C-10 DSP56009 User’s Manual MOTOROLA...
Page 253: Introduction
S/SONY CONSUMER Stereo D/A AUDIO DSP Right rear S/SONY Stereo A/D REC1 S/SONY Left effects GPIO EXTAL Stereo D/A Right effects HOST PROCESSOR External Sinusoidal Clock Source AA0259k Figure C-1 Topology of DSP Typical Audio Application MOTOROLA DSP56009 User’s Manual...
Page 254: Typical Audio Application
Application Examples TYPICAL AUDIO APPLICATION Figure C-2 depicts a sample configuration using the DSP56009 for AC3 Surround or DTS. Host Microcontroller Right Stereo DAC Left SAI Tx Center DSP56009 Stereo DAC ICE 958 Rx SAI Rx SAI Tx Subwoofer SAI Tx...
Page 255: Program Overlay
; load base address movep #(T_dly-1),x:EOR0 ; read trigger for delayed sample movep x:SAMPLE,x:EDWR0 ; write trigger for current sample movep x:EBAR0,y:Delay_Base ; store updated base address ; nop or other movep x:EDRR0,y0 ; read the delayed data MOTOROLA DSP56009 User’s Manual...
Page 256: Early Reflection Filter
; write current sample to delay line. ; EWOR = 0 ; nop or other movep x:EDRR0,x1 ; read last data macr x1,y0,a ; compute the output movep x:EBAR0,y:FIR_Base ; store FIR base move a,x:FIR_output ; store result in internal memory DSP56009 User’s Manual MOTOROLA...
Page 257: Two Channel Comb Filter
; load left channel output y0,b y;(r2)+,y0 x:(r4),a ; get right sample and gain values movep x:EBAR1,y:(r0)+ ; update base address (right) ; point (#2} ; insert “nop or other” ; instructions if required MOTOROLA DSP56009 User’s Manual...
Page 258 ; point (#3} ; insert “nop or other” ; instructions if required ; nop or other ; nop or other end comb move x1,b x0,b y1,y:out_left ; store left output move b,x:out_right ; store right output DSP56009 User’s Manual MOTOROLA...
Page 259 Delay T Comb Filters for One Channel Base Base Buffers Buffers (Left) (Right) Offset Offset Buffers Buffers (Left) (Right) Gain Gain Buffers Buffers (Left) (Right) Sample Sample (Right) (Left) AA0448 Figure C-4 Two-Channel Comb Filter Structure MOTOROLA DSP56009 User’s Manual...
Page 260: 3-Tap Fir Filter
; get G3, wait 4 (DRAM)or 2 (SRAM) inst. cycles ; or do other tasks movep x:EDRR0,y0 ; get x(n-T3) movep x:SAMPLE,x:EDWR0 ; store x(n) in mem. x0,y0,a ; calculate y(n) = y(n) + G3 x(n-T3) C-10 DSP56009 User’s Manual MOTOROLA...
Page 261 Delay T2 Delay T3 Gain G1 Gain G2 Gain G3 y(n) = G1 x (n - T1) + G2 x (n - T2) + G3 x (n - T3) AA0449 Figure C-5 3 Tap FIR Filter MOTOROLA DSP56009 User’s Manual C-11...
Page 262 Application Examples C-12 DSP56009 User’s Manual MOTOROLA...
Page 263 Absolute Addressing 4-30 Timing 4-35 Absolute Word Storage Locations 4-15 Timing Requirements 4-35 Refresh 4-31 DRAM Word Address to Physical Address Refresh Timing 4-35 Mapping 4-28 Relative Addressing 4-27 Relative Word Storage Locations 4-14 Timing 4-19 ECSR MOTOROLA DSP56009 User’s Manual Index-1...
Page 264 Receive Interrupt Enable Bits 5-17 ERTS (EMI Read Trigger Select) 4-19 SHI Control/Status Register 5-13 ESTM0-ESTM3 (EMI SRAM Memory HDM0-HDM5 (HCKR Divider Modulus Timing) 4-20 Select) 5-12 EWL0-EWL2 (EMI Word Length) 4-11 HEN (HCSR SHI Enable) 5-13 Index-2 DSP56009 User’s Manual MOTOROLA...
Page 265 Operating Modes — See Section 3 I2S Format 1-19 Input/Output 1-16 Instruction Set Summary B-7 Inter Integrated Circuit Bus 1-18 PCTL (PLL Control Register) B-17 Internal Exception Priorities PEN (PLL Enable) 2-7 SHI 5-7 Peripheral Memory Map 1-16 MOTOROLA DSP56009 User’s Manual Index-3...
Page 266 Programming 6-12 RLRS (RCS Receiver Left Right Selection) 6-12 Receiver Data Word Truncation (RDWT) RMST (RCS Receiver Master) 6-11 Programming 6-14 RRDF (RCS Receiver Right Data Full) 6-16 Receiver Left Right Selection (RLRS) Programming 6-12 Index-4 DSP56009 User’s Manual MOTOROLA...
Page 267 Clock Control Register—DSP Side 5-9 Host Transmit Data Empty 5-17 Clock Generator 5-5 Host Transmit Underrun Error 5-17 Control/Status Register—DSP Side 5-13 Receive Interrupt Enable 5-16 Data Size 5-14 Master Mode 5-25 Exception Priorities 5-7 Slave Mode 5-24 MOTOROLA DSP56009 User’s Manual Index-5...
Page 268 Control) 6-18 TX0, TX1 and TX2 (SAI Transmit Data Registers) 6-23 TXIE (TCS Transmitter Interrupt Enable) 6-21 TXIL (TCS Transmitter Interrupt Location) 6-22 Typical DSP56004/007 System Topology C-3 X Data Memory 1-15 Y Data Memory 1-15 MOTOROLA DSP56009 User’s Manual Index-6...
Page 269 APPENDIX C APPLICATION EXAMPLES MOTOROLA DSP56009 User’s Manual...
Page 270 TWO CHANNEL COMB FILTER ..... . C-7 3-TAP FIR FILTER ....... C-10 DSP56009 User’s Manual MOTOROLA...
Page 271: Introduction
S/SONY CONSUMER Stereo D/A AUDIO DSP Right rear S/SONY Stereo A/D REC1 S/SONY Left effects GPIO EXTAL Stereo D/A Right effects HOST PROCESSOR External Sinusoidal Clock Source AA0259k Figure C-1 Topology of DSP Typical Audio Application MOTOROLA DSP56009 User’s Manual...
Page 272: Typical Audio Application
Application Examples TYPICAL AUDIO APPLICATION Figure C-2 depicts a sample configuration using the DSP56009 for AC3 Surround or DTS. Host Microcontroller Right Stereo DAC Left SAI Tx Center DSP56009 Stereo DAC ICE 958 Rx SAI Rx SAI Tx Subwoofer SAI Tx...
Page 273: Program Overlay
; load base address movep #(T_dly-1),x:EOR0 ; read trigger for delayed sample movep x:SAMPLE,x:EDWR0 ; write trigger for current sample movep x:EBAR0,y:Delay_Base ; store updated base address ; nop or other movep x:EDRR0,y0 ; read the delayed data MOTOROLA DSP56009 User’s Manual...
Page 274: Early Reflection Filter
; write current sample to delay line. ; EWOR = 0 ; nop or other movep x:EDRR0,x1 ; read last data macr x1,y0,a ; compute the output movep x:EBAR0,y:FIR_Base ; store FIR base move a,x:FIR_output ; store result in internal memory DSP56009 User’s Manual MOTOROLA...
Page 275: Two Channel Comb Filter
; load left channel output y0,b y;(r2)+,y0 x:(r4),a ; get right sample and gain values movep x:EBAR1,y:(r0)+ ; update base address (right) ; point (#2} ; insert “nop or other” ; instructions if required MOTOROLA DSP56009 User’s Manual...
Page 276 ; point (#3} ; insert “nop or other” ; instructions if required ; nop or other ; nop or other end comb move x1,b x0,b y1,y:out_left ; store left output move b,x:out_right ; store right output DSP56009 User’s Manual MOTOROLA...
Page 277 Delay T Comb Filters for One Channel Base Base Buffers Buffers (Left) (Right) Offset Offset Buffers Buffers (Left) (Right) Gain Gain Buffers Buffers (Left) (Right) Sample Sample (Right) (Left) AA0448 Figure C-4 Two-Channel Comb Filter Structure MOTOROLA DSP56009 User’s Manual...
Page 278: 3-Tap Fir Filter
; get G3, wait 4 (DRAM)or 2 (SRAM) inst. cycles ; or do other tasks movep x:EDRR0,y0 ; get x(n-T3) movep x:SAMPLE,x:EDWR0 ; store x(n) in mem. x0,y0,a ; calculate y(n) = y(n) + G3 x(n-T3) C-10 DSP56009 User’s Manual MOTOROLA...
Page 279 Delay T2 Delay T3 Gain G1 Gain G2 Gain G3 y(n) = G1 x (n - T1) + G2 x (n - T2) + G3 x (n - T3) AA0449 Figure C-5 3 Tap FIR Filter MOTOROLA DSP56009 User’s Manual C-11...
Page 280 Application Examples C-12 DSP56009 User’s Manual MOTOROLA...
Page 281 Absolute Addressing 4-30 Timing 4-35 Absolute Word Storage Locations 4-15 Timing Requirements 4-35 Refresh 4-31 DRAM Word Address to Physical Address Refresh Timing 4-35 Mapping 4-28 Relative Addressing 4-27 Relative Word Storage Locations 4-14 Timing 4-19 ECSR MOTOROLA DSP56009 User’s Manual Index-1...
Page 282 Receive Interrupt Enable Bits 5-17 ERTS (EMI Read Trigger Select) 4-19 SHI Control/Status Register 5-13 ESTM0-ESTM3 (EMI SRAM Memory HDM0-HDM5 (HCKR Divider Modulus Timing) 4-20 Select) 5-12 EWL0-EWL2 (EMI Word Length) 4-11 HEN (HCSR SHI Enable) 5-13 Index-2 DSP56009 User’s Manual MOTOROLA...
Page 283 Operating Modes — See Section 3 I2S Format 1-19 Input/Output 1-16 Instruction Set Summary B-7 Inter Integrated Circuit Bus 1-18 PCTL (PLL Control Register) B-17 Internal Exception Priorities PEN (PLL Enable) 2-7 SHI 5-7 Peripheral Memory Map 1-16 MOTOROLA DSP56009 User’s Manual Index-3...
Page 284 Programming 6-12 RLRS (RCS Receiver Left Right Selection) 6-12 Receiver Data Word Truncation (RDWT) RMST (RCS Receiver Master) 6-11 Programming 6-14 RRDF (RCS Receiver Right Data Full) 6-16 Receiver Left Right Selection (RLRS) Programming 6-12 Index-4 DSP56009 User’s Manual MOTOROLA...
Page 285 Clock Control Register—DSP Side 5-9 Host Transmit Data Empty 5-17 Clock Generator 5-5 Host Transmit Underrun Error 5-17 Control/Status Register—DSP Side 5-13 Receive Interrupt Enable 5-16 Data Size 5-14 Master Mode 5-25 Exception Priorities 5-7 Slave Mode 5-24 MOTOROLA DSP56009 User’s Manual Index-5...
Page 286 Control) 6-18 TX0, TX1 and TX2 (SAI Transmit Data Registers) 6-23 TXIE (TCS Transmitter Interrupt Enable) 6-21 TXIL (TCS Transmitter Interrupt Location) 6-22 Typical DSP56004/007 System Topology C-3 X Data Memory 1-15 Y Data Memory 1-15 MOTOROLA DSP56009 User’s Manual Index-6...

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